參數(shù)資料
型號(hào)： SAA5281
廠商： NXP Semiconductors N.V.
英文描述： Integrated Video input processor and Teletext decoder IVT1.8
中文描述： 集成視頻輸入處理器和圖文電視解碼器IVT1.8
文件頁數(shù)： 22/48頁
文件大小： 1187K
代理商： SAA5281
1996 Nov 04
22
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Notes to Table 7
1.
The dash (
) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2.
Certain registers are auto-incremented following an I
2
C-bus transmission byte. These are Register R0 to R3,
R4 to R7 and R8 to R12 or R13.
3.
All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.
4.
All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but all pages are on hold.
Table 8
Register description
REGISTER BIT D0 TO D7
FUNCTION
R0 AVANCED CONTROL - auto-increments to Register 1
R11/R11B SELECT
VCR MODE
DISABLE ODD/EVEN
CBB SLAVE SYNC
Selects reading of R11 if LOW or R11B if HIGH.
If logic 1 selects short time constant mode of PLL.
Forces ODD/EVEN output LOW when logic 1 (see Table 9).
When set will modify internal slave sync timing to allow connection to sandcastle of
Philips one-chip TV IC (TDA8362).
Stops the display update of rolling time and green rolling header during page
requests when logic 1. Time updates on page reception only.
If logic 1 then ODD/EVEN output only active when no TV picture displayed
(see Table 9).
Will force the display PLL to free run at 6 MHz when logic 1.
Automatic display of FASTEXT prompt row when logic 1. Will also cause Row 24
data transmitted by packet 26 to be written to display, rather than extension
memory.
DISABLE HDR ROLL
AUTO ODD/EVEN
FREE RUN PLL
X/24 POS
R1 MODE - auto-increments to Register 2
T0, T1
TCS ON
DEW/FULL FIELD
EXT PKT ENABLE
ACQ ON/OFF
7 + P/8-BIT
VCS TO SCS
Interlace/non-interlace 312/313 line control (see Table 10).
Text composite sync or direct sync select (see Table 10 for FFB mode selection).
Field-flyback or full-channel mode.
Enables reception and storage of extension packets when logic 1.
Acquisition circuits turned off when logic 1.
7 bits with parity checking or 8-bit mode.
Connects VCS from video sync separator to display field sync detector to enable
stable display of 60 Hz status messages when logic 1.
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3
SC0 to SC2
0
ACQ CCT A0, A1
BANK SELECT A2
HAM CHECK 27, 8/30
Start column for page request data (see Table 11).
Must be logic 0 for normal operation.
Selects one of four acquisition circuits.
Selects bank of four pages being addressed for acquisition.
8/4 Hamming check packet 27 and 8/30 data.
R3 PAGE REQUEST DATA - does not auto-increment
PRD0 to PRD4
See Table 11.
相關(guān)PDF資料
PDF描述
SAA5281GP RES 11.3K OHM 1/16W .5% 0603 SMD
SAA5281P Integrated Video input processor and Teletext decoder IVT1.8
SAA5281ZP Integrated Video input processor and Teletext decoder IVT1.8
SAA5284GP Multimedia video data acquisition circuit
SAA5284 Multimedia video data acquisition circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA5281GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8
SAA5281P 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8
SAA5281ZP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8
SAA5284 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia video data acquisition circuit
SAA5284GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia video data acquisition circuit
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*