參數(shù)資料
型號(hào)： SAA4979H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Sample rate converter with embedded high quality dynamic noise reduction and expansion port
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 28 X 28 X 3.40 MM, PLASTIC, QFP-128
文件頁(yè)數(shù)： 26/52頁(yè)
文件大?。?/td> 224K
代理商： SAA4979H
2002 May 28
26
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
SAA4979H
023B
0 to 2
3 to 7
0 to 7
0 to 7
0 to 7
0 to 1
2 to 3
4 to 7
fl (MSBs)
hp1
dsplock_vstart
dsplock_vstop
dsplock_vstart (MSBs)
dsplock_vstop (MSBs)
display field length (higher 3 of 11 bits)
reserved
frame synchronization pulse position; 4 pixels resolution
display locking window vertical start (lower 8 of 10 bits)
display locking window vertical stop (lower 8 of 10 bits)
display locking window vertical start (higher 2 of 10 bits)
display locking window vertical stop (higher 2 of 10 bits)
reserved
023C
023D
023E
023F
Host address 0287H to 028DH (panoramic zoom)
0287
0288
0289
028A
028B
028C
028D
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0
1
2 to 3
4 to 7
c2
c0
hshift (LSBs)
hshift (MSBs)
nrln
nrpx_div4
transparent_mode
c0 (MSB)
nrln (MSBs)
compression or expansion non-linearity value
linear compression or expansion value (lower 8 of 9 bits)
horizontal pixel shift (lower 8 of 16 bits)
horizontal pixel shift (higher 8 of 16 bits)
number of lines per field (lower 8 of 10 bits)
number of pixels per line divided-by-4
bypass panoramic zoom: 0 = panoramic zoom active, 1 = bypass
linear compression or expansion value (MSB)
number of lines per field (higher 2 of 10 bits)
reserved
Host address 0280H to 0284H and 0290H (mid-end control)
0280
0281
0282
0283
0284
0 to 7
0 to 7
0 to 7
0 to 7
0 to 1
2 to 3
4 to 5
6 to 7
0
1
2
mid_hstart
bw_hstop
bw_hstart
bw_hstop
bw_hstart (MSBs)
bw_hstop (MSBs)
bw_hstart (MSBs)
bw_hstop (MSBs)
bypass_downsampling
mid_uv_inv
bypass_FSRC
bandwidth detection window horizontal start (lower 8 of 10 bits)
bandwidth detection window horizontal stop (lower 8 of 10 bits)
bandwidth detection window vertical start (lower 8 of 10 bits)
bandwidth detection window vertical stop (lower 8 of 10 bits)
bandwidth detection window horizontal start (higher 2 of 10 bits)
bandwidth detection window horizontal stop (higher 2 of 10 bits)
bandwidth detection window vertical start (higher 2 of 10 bits)
bandwidth detection window vertical stop (higher 2 of 10 bits)
bypass downsampling: 0 = downsampling active, 1 = bypass
inverts UVO output signals: 0 = no inversion, 1 = inversion
bypass Fixed Sample Rate Converter (FSRC): 0 = FSRC active,
1 = bypass
reserved
0290
3 to 7
Host address 0298H to 029FH (back-end control)
0298
0299
029A
029B
0 to 7
0 to 7
0 to 7
0 to 7
be_hstart
be_hstop
be_hstart
be_hstop
back-end window horizontal start (lower 8 of 10 bits)
back-end window horizontal stop (lower 8 of 10 bits)
back-end window vertical start (lower 8 of 10 bits)
back-end window vertical stop (lower 8 of 10 bits)
HOST
ADDRESS
(HEX)
BIT
NAME
DESCRIPTION
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