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參數(shù)資料
| 型號： | SAA4979H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Sample rate converter with embedded high quality dynamic noise reduction and expansion port |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 28 X 28 X 3.40 MM, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 20/52頁 |
| 文件大小： | 224K |
| 代理商： | SAA4979H |
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2002 May 28
20
Philips Semiconductors
Product specification
Sample rate converter with embedded high quality
dynamic noise reduction and expansion port
SAA4979H
The SNERT interface transforms the parallel data from the
microcontrollerinto1 or 2 MbaudSNERTdata,switchable
via microcontroller. The SNERT-bus consists of three
signals: SNCL used as serial clock signal, generated by
theSNERTinterface;SNDAusedasbidirectionaldataline
and SNRST used as reset signal, generated by the
microcontroller at port pin P1.0 to indicate the start of a
transmission.
The read or write operation must be set by the
microcontroller. When writing to the bus, 2 bytes are
loaded by the microcontroller: one for the address, the
other for the data. When reading from the bus, one byte is
loaded by the microcontroller for the address, the received
byte is the data from the addressed SNERT location.
7.5.4
I/O
PORTS
A parallel 8-bit I/O port (P1) is available, where P1.0 is
used as SNERT reset signal (SNRST), P1.2 to P1.5 can
be used for application specific control signals, and P1.6
and P1.7 are used as I
2
C-bus signals (SCL and SDA).
7.5.5
W
ATCHDOG TIMER
The microcontroller contains an internal Watchdog timer,
which can be activated by setting the corresponding
special function register PCON.4. Only a synchronous
reset will clear this bit. To prevent a system reset the
Watchdog timer must be reloaded within a specified time.
The Watchdog timer contains an 11-bit prescaler and is
therefore incremented every 0.768 ms (16 MHz clock).
The time interval between the timers reloading and the
occurrence of a reset depends on the reloaded 8-bit value.
7.5.6
R
ESET
A reset is accomplished by holding the RST pin HIGH for
at least 0.75
μ
s while the display clock is running and the
supply voltage is stabilized.
7.6
System controller
The system controller provides all necessary internal read
and write signals for controlling the embedded field
memory. The required control signals (REO and IE) for
applications with motion compensation circuits and the
drive signals (HD and VD) for the horizontal and vertical
deflection power stages are also generated.
The system controller also supports double window or
picture-in-picture processing in combination with an
external field memory by providing the required memory
control signals (RE2, RSTW2 and OIE2).
The system controller is connected to the microcontroller
via the host interface.
7.6.1
R
EAD ENABLE OUTPUT
The Read Enable Output (REO) signal is intended for
control of an external feature IC. It is a composite signal
consistingofahorizontalandaverticalpart.Thehorizontal
and vertical positions are programmable (control inputs:
reo_hstart, reo_hstop, reo_vstart and reo_vstop).
7.6.2
R
EAD ENABLE INPUT
The Read Enable Input (REI) signal is used in applications
with external feature ICs connected to the expansion port.
It has to be provided by the external circuit (see
Section 7.3.2).
7.6.3
I
NPUT ENABLE
The Input Enable (IE) signal is intended for control of field
memories in applications together with an external feature
IC connected to the expansion port. It can be directly set
or reset via the microcontroller.
7.6.4
H
ORIZONTAL DEFLECTION
The Horizontal Deflection (HD) signal is for driving a
deflection circuit; start and stop values of the horizontal
positionareprogrammableinaresolutionof4 clockcycles
(control inputs: hd_start and hd_stop).
7.6.5
V
ERTICAL DEFLECTION
The Vertical Deflection (VD) signal is for driving a
deflection circuit. This signal has a cycle time of 10 ms and
the start and stop values of the vertical position are
programmable in steps of 16
μ
s (control inputs: vd_start
and vd_stop).
7.6.6
A
UXILIARY DISPLAY SIGNAL
The Auxiliary Display Signal (ADS) is for general
purposes; the horizontal and vertical positions are
programmable (control inputs: ads_hstart, ads_hstop,
ads_vstart and ads_vstop).
7.6.7
R
EAD ENABLE
2
The Read Enable 2 (RE2) signal is intended for control of
an external field memory at input channel 2 in
picture-in-picture applications. It is a composite signal
consistingofahorizontalandaverticalpart.Thehorizontal
and vertical positions are programmable (control inputs:
re2_hstart, re2_hstop, re2_vstart and re2_vstop).
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