1997 Jun 10
4
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
HRD
V
DD1
SWC1
SRC
SDP
SWC05
IE1
WE1
STROBE
V
DD2
HRA/BLNA
1
2
3
4
5
6
7
8
9
O
horizontal reference signal output (display PLL)
supply voltage 1
serial write clock output for memory 1
serial read clock output
select deflection processor input
serial write clock output, SWC1 divided-by-2
input enable signal output (memory 1)
write enable signal output (memory 1)
strobe signal input
supply voltage 2
horizontal reference signal output (acquisition part)/horizontal blanking
signal input, reset for horizontal acquisition counters (acquisition part)
ground 1
line-locked clock signal input (acquisition part)
input enable signal output (memory 2)
write enable signal output (memory 2)
horizontal signal output (acquisition part)
horizontal, vertical or composite blanking signal output (display part)
read enable signal output (memory 1)
read enable signal output (memory 2)
horizontal blanking signal output (display part)
address latch enable signal input
write/read data signal input
supply voltage 3
ground 2
data input/output signal bit 0
data input/output signal bit 1
data input/output signal bit 2
data input/output signal bit 3
data input/output signal bit 4
data input/output signal bit 5
data input/output signal bit 6
data input/output signal bit 7 (MSB = Most Significant Bit)
line-locked clock signal input (deflection part)
ground 3
horizontal reference signal output (deflection part)
supply voltage 4
horizontal synchronization signal output (deflection part)
vertical synchronization signal output (deflection part)
vertical synchronization signal input (acquisition part)
supply
O
O
I
O
O
O
I
supply
I/O
10
11
V
SS1
LLA
IE2
WE2
CLV
HVCD
RE1
RE2
BLND
ALE
WRD
V
DD3
V
SS2
P0
P1
P2
P3
P4
P5
P6
P7
LLDFL
V
SS3
HRDFL
V
DD4
HDFL
VDFL
VACQ
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
I
O
O
O
O
O
O
O
I
I
supply
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
supply
O
O
I