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參數(shù)資料
| 型號： | SAA4952WP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Memory controller |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, SOT-187, LCC-44 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 159K |
| 代理商： | SAA4952WP |
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1997 Jun 10
14
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
Description of the acquisition part
LLA
This is the main input clock pulse for the acquisition part of
the memory controller normally generated by an external
PLL circuit. Depending on the chosen system application
LLA operates on the different frequencies of 12, 13.5, 16
and 18 MHz. When SDAF = 1 these frequencies are
doubled to 24, 27, 32 and 36 MHz. The PLL circuit is
controlled by the Analog Burst Key pulse (ABK) provided
by an inserted synchronization circuit (i.e. TDA2579 or
TDA9141) and the horizontal reference signal (HRA)
supplied by the SAA4952WP.
SWC1
The acquisition clock input signal LLA is connected via the
memory controller circuit SAA4952WP. LLA is internally
buffered and output as serial write clock for memory 1.
Additionally SWC1 is used as a clock signal for the
analog-to-digital converter (e.g. TDA8755).
SWC05
The signal SWC05 is obtained by dividing the clock LLA by
a factor of two. SWC05 is needed for feature concepts
containing new IC generations such as PALplus, LIMERIC
or PAN-IC.
HRA/BLNA
The horizontal reference output pulse (HRA) is used as the
digital feedback pulse for the phase comparator of the
acquisition PLL. The duty cycle of the signal is 50%.
The positive edge of HRA indicates the internal counter
reset.
When the memory controller operates in a digital
environment, a horizontal reference signal (BLNA) and a
suitable acquisition clock pulse have to be supplied from
the externally used circuits (i.e. SAA7151A, DMSD and
SAA7157, CGC). The rising edge of BLNA resets the
internal horizontal acquisition counters of the
SAA4952WP.
CLV
The horizontal video clamping output pulse is generated
by the acquisition clock signal LLA and can be used as a
clamp pulse for the incoming luminance and chrominance
signals Y, U and V for the analog-to-digital converter.
The time reference of CLV is the LOW-to-HIGH transition
of the HRA signal. In comparison to the SAA4951WP the
signal CLV has no internal influence on the vertical
processing and is free programmable.
WE1
A HIGH level on this output pin enables picture data to be
written to field memory 1. WE1 is a composite signal,
which includes the horizontal write enable signal (HWE1)
and the vertical write enable signal (VWE1). The position
of HWE1 can be programmed without restrictions.
It is possible to delay the horizontal timing of WE1 by up to
three LLA clock cycles. WE1 operates at a vertical
frequency of 50/60 Hz.
IE1
This output signal is used as a data input enable for
memory 1. A logic HIGH level on this output pin enables
the data information to be written into field memory 1.
The still picture function is controlled via signal IE1. When
this mode is selected, IE1 is switched to a LOW level. It is
possible to disable the still picture mode with externally
supplied STROBE pulses. Using this function a live PIP
insertion into a frozen main picture is possible, as the write
pointer of memory 1 is still incremented, depending on the
level of WE1. The STROBE input is not sampled in the
controller. This means that the display part of the PIP
module should be synchronized to the IPQ write clock.
HVACQS
The vertical synchronization signal for the acquisition part
(VACQ) is sampled by the pulse HVACQS twice per line.
This signal consists of the two programmable pulses
HVACQS1 and HVACQS2 (see Fig.4). To ensure a save,
sampling the position of each pulse (two per line) can be
programmed in steps of four LLA clock cycles. The signal
is referenced to the rising edge of HRA.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA4955 | 2.9-Mbit field memory |
| SAA4955TJ | 2.9-Mbit field memory |
| SAA4956TJ | 2.9-Mbit field memory with noise reduction |
| SAA4960 | Integrated PAL comb filter |
| SAA4963 | Integrated NTSC comb filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4955 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory |
| SAA4955TJ | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory |
| SAA4956TJ | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.9-Mbit field memory with noise reduction |
| SAA4960 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated PAL comb filter |
| SAA4963 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated NTSC comb filter |
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