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參數(shù)資料
| 型號： | SAA2023GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 41/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA2023GP |
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May 1994
41
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
Scratch pad RAM
The SAA2023 provides the microcontroller with a scratch
pad RAM that the microcontroller can use for whatever it
likes. The size of the scratch pad depends upon the size
and type of RAM used with the SAA2023. The locations in
the scratch pad RAM may be written and read in 8 bit or
12 bit units.
The RAM may be viewed as having up to 4 quarters, the
availability of these quarters for the scratch pad RAM is
given in Table 44.
Table 44
Availability of RAM quarters for the scratch pad RAM.
Note
1.
In RAM quarter YZ = 00, the scratch pad is arranged as 6 pages, where each page consists of 7 columns
×
64 rows.
The pages are numbered
0 to 5
, the columns
1 to 7
and the rows
0 to 63
.
This gives a total of (6
×
7
×
64) 2688 locations.
In each of the RAM quarters YZ = 01, 10 and 11 the scratch pad is arranged as 6 pages where each page consists
of 8 columns
×
448 rows. The pages are numbered
0 to 5
, the columns
0 to 7
and the rows
0 to 447
. This gives then
a total of (6
×
8
×
448) 21504 locations per RAM quarter YZ.
RTYPE
TYPE OF RAM USED
AVAILABLE RAM QUARTERS YZ
(1)
1
0
0
0
0
1
1
1
0
0
1
0
1
1
DRAM 64K
×
4
DRAM 256K
×
4
SRAM 32K
×
8 fast
SRAM 128K
×
8 fast
SRAM (2
×
) 32K
×
8 slow
SRAM 128K
×
8 slow
00
00, 01, 10 and 11
00
00, 01, 10 and 11
00
00 and 10
During communication with the scratch pad RAM, the
RAM quarter YZ is chosen when sending the RDDRAC,
RDWDRAC, WRDRAC or WRWDRAC commands to the
TFE module.
Use of the scratch pad RAM outside the specified ranges
is not allowed and it may upset the operation of the
SAA2023.
As with SYSINFO and AUX transfers can occur at high
speed at all times except the second half of time
segment 0, that is when the status bit SLOWTFR is HIGH.
When SLOWTFR is HIGH the microcontroller must poll the
status bit RFBT to investigate when a transfer can occur.
Two addressing modes are available for the scratch pad,
namely random access and auto-increment. For random
access mode the address of each location is sent by the
microcontroller to the SAA2023 before each location
transfer. For auto-increment mode the address of the first
location is sent by the microcontroller before the first
location transfer, auto-incrementing of the row occurs then
for all transfers until the end of the column.
The 8 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 1 byte per
memory location, therefore the byte counter will increment
after each byte transfer.
The 12 bit transfers are initiated by the WRDRAC and
RDDRAC commands, these transfers are each 2 bytes
per memory location. The first byte contains the 4 Most
Significant Bits (MSBs) of the memory location in its
4 Least Significant Bits (LSBs) positions. The other bit
positions being ‘don’t care’. The second byte contains the
8 LSBs of the memory location. The byte counter is
incremented after the transfer of the second byte.
The RACCNT and BYTCNT registers are used for
addressing the scratch pad.
For RAM quarter YZ = 00 the mapping of the scratch pad
RAM address onto the RACCNT and BYTCNT registers is
shown in Table 45.
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