參數(shù)資料
型號: SAA2023GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Drive processor for DCC systems
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80
文件頁數(shù): 34/56頁
文件大小: 274K
代理商: SAA2023GP
May 1994
34
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
ANAEYE register
Table 28
ANAEYE register analog eye pattern selection register.
Notes
1.
AEN analog eye pattern output enable. If this bit is LOW the Digital-to-Analog Converter (DAC) is switched off and
the output is HIGH.
ACHN3 to ACHN0 select channel for analog eye output.
2.
Table 29
ACHN3 to ACHN0 channel selections for analog eye output.
T1sel register
Table 30
T1SEL register CHTST1 pin selection register.
Table 31
T1C3 to T1C0 CHTST1 pin channel selections.
BIT
7
0
6
0
5
0
4
3
2
1
0
Meaning
Default
AEN
(1)
0
ACHN3
(2)
0
ACHN2
(2)
0
ACHN1
(2)
0
ACHN0
(2)
0
ACHN
CHANNEL ON ANAEYE
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
AUX
BIT
7
0
6
5
4
3
2
1
0
Meaning
Default
T1F2
0
T1F1
0
T1F0
0
T1C3
0
T1C2
0
T1C1
0
T1C0
0
T1C
CHANNEL ON CHTST1
3
2
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
AUX
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