參數(shù)資料
型號： SAA2023GP
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Drive processor for DCC systems
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80
文件頁數(shù)： 17/56頁
文件大?。?/td> 274K
代理商： SAA2023GP
May 1994
17
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
RAM connections
The SAA2023 has been designed to operate with DRAMs
and SRAMs. Suitable DRAMs are 64K
×
4-bit or
256K
×
4-bit configurations operating in page mode, with
an access time of 80 to 100 ns. The timing for read, write
and refresh cycles for DRAMs is shown in Figs 10 to 12.
The timing for SRAMs is shown in Figs 13 to 19.
For fast SRAMs: (these values are subject to verification
during characterization). The conditions (most critical at
the required V
DD
) are shown in Table 14.
Table 14
Fast SRAM conditions.
Note
1.
The SAA2023 should work in: RType = ‘01’;
RTim = ‘00’ mode.
A9/CAS
When SAA2023 is used with SRAM this output pin is
Address line 9, and should be connected directly to the
corresponding address pin on the SRAM. When SAA2023
is used with DRAM this output pin is the column address
strobe (active LOW), it connects directly to the column
address strobe pin of the DRAM.
A10/RAS
When SAA2023 is used with SRAM this output pin is
Address line 10, and should be connected to the
corresponding address pin of the SRAM. When SAA2023
is used with DRAM this output pin is the row address
strobe (active LOW), it connects directly to the row
address strobe pin of the DRAM.
CONDITION
(1)
TIME
Write pulse duration
Data set-up to rising WEN
Write cycle time
Read access time
t
W
≤
140 ns
t
su
≤
72 ns
T
cy
≤
200 ns
t
ACC
≤
240 ns
OEN
This output pin is the output enable (active LOW) for the
RAM, it connects directly to the output enable pin of the
RAM.
WEN
This output pin is the write enable (active LOW) for the
RAM, it connects directly to the write enable pin of the
RAM.
A0
TO
A8
When SAA2023 is used with DRAM these output pins are
the multiplexed column and row address lines. When the
64K
×
4-bit DRAM is used, pins A0 to A7 should be
connected to the DRAM address input pins, and pin A8
should be left unconnected. When using the 256K
×
4-bit
DRAM the address pins A0 to A8 should be connected to
the address input pins of the DRAM.
When SAA2023 is used with SRAM these are the lower
address pins and should be connected directly to the
SRAM address pins.
A11
This output pin is the an address pin for the SRAM and
when SRAM is used they should be connected directly to
the address pins of the SRAM. When DRAM is used this
pin should not be connected.
A10
AND
A12
TO
A16
These output pins are the upper address pins for the
SRAM and when SRAM is used they should be connected
directly to the address pins of the SRAM. When DRAM is
used or when the small SRAM is used all or some of these
pins become available as Port expander outputs.
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