388
32072H–AVR32–10/2012
AT32UC3A3
1)
The reset value for these registers are device specific. Please refer to the Module Config-
uration section at the end of this chapter.
2)
The reset value is undefined depending on the pin states.
20.6.1
Access Types
Each configuration register can be accessed in four different ways. The first address location
can be used to write the register directly. This address can also be used to read the register
value. The following addresses facilitate three different types of write access to the register. Per-
forming a “set” access, all bits written to one will be set. Bits written to zero will be unchanged by
the operation. Performing a “clear” access, all bits written to one will be cleared. Bits written to
zero will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits
written to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.
IFR), not all access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
0xB4
Interrupt Mode Register 1
Set
IMR1S
Write-Only
0xB8
Interrupt Mode Register 1
Clear
IMR1C
Write-Only
0xBC
Interrupt Mode Register 1
Toggle
IMR1T
Write-Only
0xC0
Glitch Filter Enable Register
Read/Write
GFER
Read/Write
(1)
0xC4
Glitch Filter Enable Register
Set
GFERS
Write-Only
0xC8
Glitch Filter Enable Register
Clear
GFERC
Write-Only
0xCC
Glitch Filter Enable Register
Toggle
GFERT
Write-Only
0xD0
Interrupt Flag Register
Read
IFR
Read-Only
(1)
0xD4
Interrupt Flag Register
-
0xD8
Interrupt Flag Register
Clear
IFRC
Write-Only
0xDC
Interrupt Flag Register
-
Table 20-1.
GPIO Register Memory Map
Offset
Register
Function
Name
Access
Reset value