803
32072H–AVR32–10/2012
AT32UC3A3
29.7.6
Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x1C
Reset Value:
0x000C0000
RXBUFF: RX Buffer Full
This bit is set when the Buffer Full signal from the Peripheral DMA is active.
This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive.
ENDRX: End of RX Buffer
This bit is set when the End Receive signal from the Peripheral DMA is active.
This bit is cleared when the End Receive signal from the Peripheral DMA is inactive.
GOVRE: General Overrun Error
This bit is set when a General Overrun Error has occurred.
This bit is cleared when the SR register is read.
1: At least one General Overrun Error has occurred since the last read of the SR register.
0: No General Overrun Error occurred since the last read of the SR register.
DRDY: Data Ready
This bit is set when a data has been converted and is available in the LCDR register.
This bit is cleared when the LCDR register is read.
0: No data has been converted since the last read of the LCDR register.
1: At least one data has been converted and is available in the LCDR register.
OVREn: Overrun Error n
These bits are set when an overrun error on the corresponding channel has occurred (if implemented).
These bits are cleared when the SR register is read.
0: No overrun error on the corresponding channel (if implemented) since the last read of SR.
1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR.
EOCn: End of Conversion n
These bits are set when the corresponding conversion is complete.
These bits are cleared when the corresponding CDR or LCDR registers are read.
0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished.
1: Corresponding analog channel (if implemented) is enabled and conversion is complete.
31
30
29
28
27
26
25
24
––––––––
23
22
21
20
19
18
17
16
––––
RXBUFF
ENDRX
GOVRE
DRDY
15
14
13
12
11
10
9
8
OVRE7
OVRE6
OVRE5
OVRE4
OVRE3
OVRE2
OVRE1
OVRE0
76543210
EOC7
EOC6
EOC5
EOC4
EOC3
EOC2
EOC1
EOC0