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型號：	S80C52CXXX-25SHXXX
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	126/1021頁
文件大小：	15196K
代理商：	S80C52CXXX-25SHXXX

32072H–AVR32–10/2012

AT32UC3A3

Coding timing parameters

All timing parameters are defined for one chip select and are grouped together in one register

according to their type.

The Setup register (SETUP) groups the definition of all setup parameters:

NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP.

The Pulse register (PULSE) groups the definition of all pulse parameters:

NRDPULSE, NCSRDPULSE, NWEPULSE, and NCSWRPULSE.

The Cycle register (CYCLE) groups the definition of all cycle parameters:

NRDCYCLE, NWECYCLE.

Table 15-4 on page 192 shows how the timing parameters are coded and their permitted range.

Usage restriction

The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP

and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre-

dictable behavior of the SMC.

For read operations:

Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the

memory interface because of the propagation delay of theses signals through external logic and

pads. If positive setup and hold values must be verified, then it is strictly recommended to pro-

gram non-null values so as to cover possible skews between address, NCS and NRD signals.

For write operations:

If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address,

byte select lines, and NCS signal after the rising edge of NWE. This is true if the MODE.WRITE-

MODE bit is written to one. See Section 15.6.5.2.

For read and write operations: a null value for pulse parameters is forbidden and may lead to

unpredictable behavior.

In read and write cycles, the setup and hold time parameters are defined in reference to the

address bus. For external devices that require setup and hold time between NCS and NRD sig-

nals (read), or between NCS and NWE signals (write), these setup and hold times must be

converted into setup and hold times in reference to the address bus.

Table 15-4.

Coding and Range of Timing Parameters

Coded Value

Number of Bits

Effective Value

Permitted Range

Coded Value

Effective Value

128 x setup[5] + setup[4:0]

≤ value ≤ 31

≤ value ≤ 63

≤ value ≤ 31

≤ value ≤ 128+31

256 x pulse[6] + pulse[5:0]

≤ value ≤ 63

≤ value ≤ 127

≤ value ≤ 63

≤ value ≤ 256+63

256 x cycle[8:7] + cycle[6:0]

≤ value ≤ 127

≤ value ≤ 255

≤ value ≤ 383

≤ value ≤ 511

≤ value ≤ 127

≤ value ≤ 256+127

≤ value ≤ 512+127

≤ value ≤ 768+127

相關(guān)PDF資料	PDF描述
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-40SHXXX:RD	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
SC-80C32E-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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