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型號：	S80C52CXXX-25SHXXX
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	727/1021頁
文件大?。?/td>	15196K
代理商：	S80C52CXXX-25SHXXX

32072H–AVR32–10/2012

AT32UC3A3

This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit.

NBUSYBK: Number of Busy Banks

This field indicates the number of busy bank.

For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are

busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.

For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this

triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.

DTSEQ: Data Toggle Sequence

This field indicates the data PID of the current bank.

For OUT pipe, this field indicates the data toggle of the next packet that will be sent.

For IN pipe, this field indicates the data toggle of the received packet stored in the current bank.

SHORTPACKETI: Short Packet Interrupt

This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).

This bit is cleared when the SHORTPACKETIC bit is written to one.

RXSTALLDI: Received STALLed Interrupt

This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe.

The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.

This bit is cleared when the RXSTALLDIC bit is written to one.

CRCERRI: CRC Error Interrupt

This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if

the TXSTPE bit is one.

This bit is cleared when the CRCERRIC bit is written to one.

OVERFI: Overflow Interrupt

This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is

triggered if the OVERFIE bit is one.

This bit is cleared when the OVERFIC bit is written to one.

NAKEDI: NAKed Interrupt

This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.

Bank2 if supported

Number of busy bank

All banks are free.

2 busy banks if supported

Data toggle sequence

Current Bank

相關(guān)PDF資料	PDF描述
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-40SHXXX:RD	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
SC-80C32E-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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