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型號(hào)：	S80C52CXXX-25SHXXX
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	453/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C52CXXX-25SHXXX

32072H–AVR32–10/2012

AT32UC3A3

Ten Bit Addressing

Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers

with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of

CMDR.SADR must be written appropriately.

In Figure 23-14 and Figure 23-15, the grey boxes represent signals driven by the master, the

white boxes are driven by the slave.

Master Transmitter

To perform a master transmitter transfer:

Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the

desired address and NBYTES value.

Figure 23-14. A Write Transfer with 10-bit Addressing

Master Receiver

When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-

trolled. CMDR.REPSAME must be written to one when the address phase of the transfer should

consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The IC standard

specifies that such addressing is required when addressing a slave for reads using 10-bit

To perform a master receiver transfer:

Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0,

NBYTES=0 and the desired address.

Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the

desired address and NBYTES value.

Figure 23-15. A Read Transfer with 10-bit Addressing

SMBus Mode

SMBus mode is enabled and disabled by writing to the SMEN and SMDIS bits in CR. SMBus

mode operation is similar to IC operation with the following exceptions:

Only 7-bit addressing can be used.

The SMBus standard describes a set of timeout values to ensure progress and throughput on

the bus. These timeout values must be written into SMBTR.

Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).

A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.

A set of addresses have been reserved for protocol handling, such as Alert Response

Address (ARA) and Host Header (HH) Address.

SLAVE ADDRESS

SLAVE ADDRESS

SLAVE ADDRESS

SLAVE ADDRESS

SLAVE ADDRESS

相關(guān)PDF資料	PDF描述
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-40SHXXX:RD	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
SC-80C32E-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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