亚洲国产免费AV片在线无码免费看,亚洲av无码电影网,久久久久精品无码三级

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25635 > S80C52CXXX-12SHXXX (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號：	S80C52CXXX-12SHXXX
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
文件頁數(shù)：	904/1021頁
文件大?。?/td>	15196K
代理商：	S80C52CXXX-12SHXXX

32072H–AVR32–10/2012

AT32UC3A3

The DMA Controller can be used in association with the AES to perform an encryption/decryp-

tion of a buffer without any action by the software during processing.

In this starting mode, the type of the data transfer (byte, halfword or word) depends on the oper-

The sequence is as follows:

Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.

Write the initialization vector (or counter) in the IVnR registers.

The Initialization Vector Registers concern all modes except ECB.

Configure a channel of the DMA Controller with source address (data buffer to

encrypt/decrypt) and destination address set to register IDATA1R (index is automatically

incremented and rolled over to write IDATAnR). Then configure a second channel with source

address set to ODATA1R (index is automatically incremented and rolled over to read

ODATAnR) and destination address to write processed data.

Transmit and receive buffers can be identical.

Enable the DMA Controller in transmission and reception to start the processing.

The processing completion should be monitored with the DMA Controller.

Last Output Data Mode

This mode is used to generate cryptographic checksums on data (MAC) by means of cipher

block chaining encryption algorithm (CBC-MAC algorithm for example).

After each end of encryption/decryption, the output data is available either on the ODATAnR

registers for manual and automatic mode or at the address specified in the receive buffer pointer

for DMA mode.

The Last Output Data bit in the Mode Register (MR.LOD) allows retrieval of only the last data of

several encryption/decryption processes.

Therefore, there is no need to define a read buffer in DMA mode.

This data is only available on the Output Data Registers (ODATAnR).

Table 33-2.

Data Transfer Type for the Different Operation Modes

Operation Mode

Data Transfer Type (DMA)

相關(guān)PDF資料	PDF描述
SC80C52XXX-12SV	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
S80C32XXX-40R	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S83C154DCXXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
SD80C32EXXX-30SC	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-12SHXXX:R	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

(若只采購一條型號，填寫一行即可)

*型號	*數(shù)量	廠商	批號	封裝