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型號(hào)：	S80C52CXXX-12SHXXX
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	831/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C52CXXX-12SHXXX

32072H–AVR32–10/2012

AT32UC3A3

The structure of commands, responses and data blocks is described in the MultiMedia-Card

System Specification. Refer also to Table 31-5 on page 828.

MultiMediaCard bus data transfers are composed of these tokens.

There are different types of operations. Addressed operations always contain a command and a

response token. In addition, some operations have a data token; the others transfer their infor-

mation directly within the command or response structure. In this case, no data token is present

in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the MCI

clock (CLK).

Two types of data transfer commands are defined:

Sequential commands: these commands initiate a continuous data stream. They are

terminated only when a stop command follows on the CMD line. This mode reduces the

command overhead to an absolute minimum.

Block-oriented commands: these commands send a data block succeeded by CRC bits.

Both read and write operations allow either single or multiple block transmission. A multiple

block transmission is terminated when a stop command follows on the CMD line similarly to the

sequential read or when a multiple block transmission has a pre-defined block count (See Sec-

The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.

Command - Response Operation

After reset, the MCI is disabled and becomes valid after setting the Multi-Media Interface Enable

bit in the Control Register (CR.MCIEN).

The Power Save Mode Enable bit in the CR register (CR.PWEN) saves power by dividing the

MCI clock (CLK) by 2PWSDIV + 1 when the bus is inactive. The Power Saving Divider field locates

in the Mode Register (MR.PWSDIV).

The two bits, Read Proof Enable and Write Proof Enable in the MR register (MR.RDPROOF and

MR.WRPROOF) allow stopping the MCI Clock (CLK) during read or write access if the internal

FIFO is full. This will guarantee data integrity, not bandwidth.

All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification.

The two bus modes (open drain and push/pull) needed to process all the operations are defined

in the Command Register (CMDR). The CMDR register allows a command to be carried out.

For example, to perform an ALL_SEND_CID command

Table 31-4.

ALL_SEND_CID command

Host Command

ID Cycles

相關(guān)PDF資料	PDF描述
SC80C52XXX-12SV	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
S80C32XXX-40R	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S83C154DCXXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
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S80C52XXX-12SHXXX:R	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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