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型號：	S80C52CXXX-12SHXXX
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
文件頁數(shù)：	706/1021頁
文件大?。?/td>	15196K
代理商：	S80C52CXXX-12SHXXX

32072H–AVR32–10/2012

AT32UC3A3

BUFFCLOSEINEN: Buffer Close Input Enable

For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB

OUT data transfer (received short packet).

For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero.

For high-speed OUT isochronous, it may make sense. In that case, if BUFFCLOSEINEN is written to one, the current DMA

transfer is closed when the received PID packet is not MDATA.

Writing a zero to this bit to disable this feature.

LDNXTCHDESCEN: Load Next Channel Descriptor Enable

1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit

0: no channel register is loaded after the end of the channel transfer.

If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN

endpoint, or endpoint is full for OUT endpoint).

Table 27-6.

DMA Channel Control Command Summary

CHEN: Channel Enable

Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is

written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both

UDDMAnSTATUS.CHEN and CHACTIVE bits are zero.

Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer. Then any pending request

will start the transfer. This may be used to start or resume any requested transfer.

This bit is cleared when the channel source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by

descriptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed.

If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the

UDDMAnSTATUS.CHEN bit is cleared.

If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer

occurs) and the next descriptor is immediately loaded.

LDNXTCHDES

Current Bank

Run and stop at end of buffer

Load next descriptor now

Run and link at end of buffer

相關(guān)PDF資料	PDF描述
SC80C52XXX-12SV	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
S80C32XXX-40R	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S83C154DCXXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
SD80C32EXXX-30SC	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-12SHXXX:R	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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