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型號(hào)：	S80C52CXXX-12SHXXX
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	298/1021頁(yè)
文件大小：	15196K
代理商：	S80C52CXXX-12SHXXX

32072H–AVR32–10/2012

AT32UC3A3

The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is

When CTLx.SRC_TR_WIDTH is less than CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit

is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single

word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel

FIFO but not enough to form a single transfer of CTLx.DST_TR_WIDTH width. In this configura-

tion, once the channel is disabled, the remaining data in the channel FIFO are not transferred to

the destination peripheral. It is permitted to remove the channel from the suspension state by

writing a ‘0’ to the CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.

If a channel is disabled by software, an active single or burst transaction is not guaranteed to

receive an acknowledgement.

Abnormal Transfer Termination

A DMACA DMA transfer may be terminated abruptly by software by clearing the channel enable

bit, ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the

ChEnReg.CH_EN bit is cleared over the HSB slave interface. Consider this as a request to dis-

able the channel. The ChEnReg.CH_EN must be polled and then it must be confirmed that the

channel is disabled by reading back 0. A case where the channel is not be disabled after a chan-

nel disable request is where either the source or destination has received a split or retry

response. The DMACA must keep re-attempting the transfer to the system HADDR that origi-

nally received the split or retry response until an OKAY response is returned. To do otherwise is

an System Bus protocol violation.

Software may terminate all channels abruptly by clearing the global enable bit in the DMACA

Configuration Register (DmaCfgReg[0]). Again, this does not mean that all channels are dis-

abled immediately after the DmaCfgReg[0] is cleared over the HSB slave interface. Consider

this as a request to disable all channels. The ChEnReg must be polled and then it must be con-

firmed that all channels are disabled by reading back ‘0’.

If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to

the destination peripheral and is not present when the channel is re-enabled. For read sensitive

source peripherals such as a source FIFO this data is therefore lost. When the source is not a

read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to

empty may be acceptable as the data is available from the source peripheral upon request and is

If a channel is disabled by software, an active single or burst transaction is not guaranteed to

receive an acknowledgement.

相關(guān)PDF資料	PDF描述
SC80C52XXX-12SV	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
S80C32XXX-40R	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S83C154DCXXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
SD80C32EXXX-30SC	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-12SHXXX:R	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C52T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C52T-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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