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型號(hào)：	S80C51C-20D
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	866/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S80C51C-20D

32072H–AVR32–10/2012

AT32UC3A3

A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data

transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line

(DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer

block length becomes free.

The NOTBUSY bit allows to deal with these different states.

1: MCI is ready for new data transfer.

0: MCI is not ready for new data transfer.

This bit is cleared at the end of the card response.

This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card.

Refer to the MMC or SD Specification for more details concerning the busy behavior.

DTIP: Data Transfer in Progress

This bit is set when the current data transfer is in progress.

This bit is cleared at the end of the CRC16 calculation

1: The current data transfer is still in progress.

0: No data transfer in progress.

BLKE: Data Block Ended

This bit must be used only for Write Operations.

This bit is set when a data block transfer has ended.

This bit is cleared when reading SR.

1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status.

0: A data block transfer is not yet finished.

Refer to the MMC or SD Specification for more details concerning the CRC Status.

TXRDY: Transmit Ready

This bit is set when the last data written in the TDR register has been transferred.

This bit is cleared the last data written in the TDR register has not yet been transferred.

RXRDY: Receiver Ready

This bit is set when the data has been received since the last read of the RDR register.

This bit is cleared when the data has not yet been received since the last read of the RDR register.

CMDRDY: Command Ready

This bit is set when the last command has been sent.

This bit is cleared when writing the CMDR register

相關(guān)PDF資料	PDF描述
S80C32XXX-16R	8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
S80C52CXXX-16	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
S80C52CXXX-25SHXXX	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C51C-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51C-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51C-36	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51C-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51FA-1	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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