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您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25635 > S80C51C-20D (ATMEL CORP) 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號(hào)：	S80C51C-20D
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	413/1021頁(yè)
文件大小：	15196K
代理商：	S80C51C-20D

32072H–AVR32–10/2012

AT32UC3A3

The address in CR.ADR is checked for address match if CR.SMATCH is one.

The General Call address is checked for address match if CR.GCMATCH is one.

In SMBus mode:

The address in CR.ADR is checked for address match if CR.SMATCH is one.

The Alert Response Address is checked for address match if CR.SMAL is one.

The Default Address is checked for address match if CR.SMDA is one.

The Host Header Address is checked for address match if CR.SMHH is one.

Clock Stretching

Any slave or bus master taking part in a transfer may extend the TWCK low period at any time.

The TWIS may extend the TWCK low period after each byte transfer if CR.STREN is one and:

Module is in slave transmitter mode, data should be transmitted, but THR is empty, or

Module is in slave receiver mode, a byte has been received and placed into the internal

shifter, but the Receive Holding Register (RHR) is full, or

Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains

stretched until all address match bits in the Status Register (SR) have been cleared.

If CR.STREN is zero and:

Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit

the value present in THR (the last transmitted byte or reset value), and set SR.URUN.

Module is in slave receiver mode, a byte has been received and placed into the internal

shifter, but RHR is full: Discard the received byte and set SR.ORUN.

If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and

the TWIS waits for a new START condition.

Slave Transmitter Mode

If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it

will enter slave transmitter mode and set the SR.TRA bit (note that SR.TRA is set one

CLK_TWIS cycle after the relevant address match bit in the same register is set).

After the address phase, the following actions are performed:

If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to

transmit. This is necessary in order to know when to transmit the PEC byte. NBYTES

can also be used to count the number of bytes received if using DMA.

Byte to transmit depends on IC/SMBus mode and CR.PEC:

– If in IC mode or CR.PEC is zero or NBYTES is non-zero: The TWIS waits until THR

contains a valid data byte, possibly stretching the low period of TWCK. After THR

contains a valid data byte, the data byte is transferred to a shifter, and then

SR.TXRDY is changed to one because the THR is empty again.

– SMBus mode and CR.PEC is one: If NBYTES is zero, the generated PEC byte is

automatically transmitted instead of a data byte from THR. TWCK will not be

stretched by the TWIS.

The data byte in the shifter is transmitted.

相關(guān)PDF資料	PDF描述
S80C32XXX-16R	8-BIT, 16 MHz, MICROCONTROLLER, PQCC44
S80C52CXXX-16	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
S80C52CXXX-25SHXXX	8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:D	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
S80C32-20SHXXX:R	8-BIT, 20 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C51C-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51C-30	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51C-36	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51C-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C51FA-1	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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