55
32000D–04/2011
AVR32
6.2.2.2
DTLB Protection Violation
An DTLB protection violation is issued if a data access violates access permissions. The violat-
ing access is not executed. The address of the failing instruction is placed on the system stack.
6.2.2.3
ITLB Miss Violation
An ITLB miss violation is issued if an instruction fetch does not hit in any region. The violating
instruction is not executed. The address of the failing instruction is placed on the system stack.
6.2.2.4
DTLB Miss Violation
An DTLB miss violation is issued if a data access does not hit in any region. The violating access
is not executed. The address of the failing instruction is placed on the system stack.
6.2.2.5
TLB Multiple Hit Violation
An access hit in multiple protection regions. The address of the failing instruction is placed on
the system stack. This is a critical system error that should not occur.
6.3
Example of MPU functionality
As an example, consider region 0. Let region 0 be of size 16 KB, thus each subregion is 1KB.
Subregion 0 has offset 0-1KB from the base address, subregion 1 has offset 1KB-2KB and so
on.
MPUAPRA and MPUAPRB each has one field per region. Each subregion in region 0 can get its
access permissions from either MPUAPRA[AP0] or MPUAPRB[AP0], this is selected by the sub-
region’s bitfield in MPUPSR0.
Let:
MPUPSR0 = {0b0000_0000_0000_0000, 0b1010_0000_1111_0101}
MPUAPRA = {A, B, C, D, E, F, G, H}
MPUAPRB = {a, b, c, d, e, f, g, h}
where {A-H, a-h} have legal values as defined in
Table 6-3.
Thus for region 0:
Table 6-4.
Example of access rights for subregions
Subregion
Access
permission
Subregion
Access
permission
0h8H
1H
9H
2h10
H
3H
11
H
4h12
H
5h13
h
6h14
H
7h15
h