115
32000D–04/2011
AVR32
ld.sh
CRd, Rp++
Load signed halfword with post-
increment.
Rd
← SE(*(Rp++))
1
C
Rd, --Rp
Load signed halfword with pre-decrement.
Rd
← SE(*(--Rp))
1
C
Rd, Rp[disp]
Load signed halfword with displacement.
Rd
← SE(*(Rp+(ZE(disp3)<<1)))
1
E
Rd, Rp[disp]
Rd
← SE(*(Rp+(SE(disp16))))
1
E
Rd, Rb[Ri<<sa]
Indexed Load signed halfword.
Rd
← SE(*(Rb+(Ri << sa2)))
1
ld.sh{cond4}
E
Rd, Rp[disp]
Load signed halfword with displacement if
condition satisfied.
if {cond4}
Rd
← SE(*(Rp+ZE(disp9<<1)))
2
ld.w
C
Rd, Rp++
Load word with post-increment.
Rd
← *(Rp++)
1
C
Rd, --Rp
Load word with pre-decrement.
Rd
← *(--Rp)
1
C
Rd, Rp[disp]
Load word with displacement.
Rd
← *(Rp+(ZE(disp5)<<2))
1
E
Rd, Rp[disp]
Rd
← *(Rp+(SE(disp16)))
1
E
Rd, Rb[Ri<<sa]
Indexed Load word.
Rd
← *(Rb+(Ri << sa2))
1
E
Rd, Rb[Ri:<part> <<
2]
Load word with extracted index into Rd.
Rd
← *(Rb+(Ri:<part> << 2))
1
ld.w{cond4}
E
Rd, Rp[disp]
Load word with displacement if condition
satisfied.
if {cond4}
Rd
← *(Rp+ZE(disp9<<2))
2
ld.d
C
Rd, Rp++
Load doubleword with post-increment.
Rd+1:Rd
← (*(Rp++))
1
C
Rd, --Rp
Load doubleword with pre-decrement.
Rd+1:Rd
← (*(--Rp))
1
C
Rd, Rp
Load doubleword.
Rd+1:Rd
← *(Rp)
1
E
Rd, Rp[disp]
Load double with displacement.
Rd+1:Rd
← *(Rp+SE(disp16))
1
E
Rd, Rb[Ri<<sa]
Indexed Load double.
Rd+1:Rd
← *(Rb+(Ri << sa2))
1
ldins.b
E
Rd:<part>, Rp[disp]
Load byte with displacement and insert at
specified byte location in Rd.
Rd:<part>
← *(Rp+(SE(disp12)))
1
ldins.h
E
Rd:<part>, Rp[disp]
Load halfword with displacement and
insert at specified halfword location in Rd.
Rd:<part>
←
*(Rp+(SE(disp12)<<1))
1
ldswp.sh
E
Rd, Rp[disp]
Load halfword with displacement, swap
bytes and sign-extend
Temp
← *(Rp+(SE(disp12) << 1)
Rd
← SE(Temp[7:0], Temp[15:8])
1
ldswp.uh
E
Load halfword with displacement, swap
bytes and zero-extend
Temp
← *(Rp+(SE(disp12) << 1)
Rd
← ZE(Temp[7:0], Temp[15:8])
1
ldswp.w
E
Load word with displacement and swap
bytes.
Temp
← *(Rp+(SE(disp12) << 2)
Rd[31:24]
← Temp[7:0],
Rd[23:16]
← Temp[15:8],
Rd[15:8]
← Temp[23:16],
Rd[7:0]
← Temp[31:24]
1
lddpc
C
Rd, PC[disp]
Load with displacement from PC.
Rd
← *((PC && 0xFFFF_FFFC)
+(ZE(disp7)<<2))
1
lddsp
C
Rd, SP[disp]
Load with displacement from SP.
Rd
← *((SP && 0xFFFF_FFFC)
+(ZE(disp7)<<2))
1
Table 9-10.
Load/Store Operations (Continued)