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SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
25.
Bus Matrix (MATRIX)
25.1 Description
The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths
between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix
interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one
cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration User
Interface with Registers that allow the Bus Matrix to support application specific features.
25.2 Embedded Characteristics
12-layer Matrix, handling requests from 11 masters
Programmable Arbitration strategy
Fixed-priority Arbitration
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
Burst Management
Breaking with Slot Cycle Limit Support
Undefined Burst Length Support
One Address Decoder provided per Master
Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for
internal flash boot, one after remap
Boot Mode Select
Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
Selection is made by General purpose NVM bit sampled at reset
Remap Command
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash)
Allows Handling of Dynamic Exception Vectors