參數(shù)資料
型號(hào): S75WS256NDFBAWLK0
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: Stacked Multi-Chip Product (MCP)
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA84
封裝: 9 X 12 MM, 1.40 MM HEIGHT, FBGA-84
文件頁(yè)數(shù): 7/15頁(yè)
文件大小: 235K
代理商: S75WS256NDFBAWLK0
October 6, 2005 S75WS-N_02_A2
S75WS-N Based MCPs
5
P r e l i m i n a r y
3
Input/Output Descriptions
Table 3.1
identifies the input and output package connections provided on the device.
Table 3.2
identifies the ORNAND input and output connections provided on the device.
Table 3.1 NOR Flash and RAM Input/Output Descriptions
Symbol
Description
A
max
– A0
Address Inputs
(Common)
DQ15 - DQ0
Data Inputs/Outputs
OE#
Output Enable input
WE#
Write Enable input
V
SS
Ground
NC
No Connect; not connected internally.
RDY
Ready output. Indicates the status of the Burst read.
(Flash)
CLK
Clock input. In burst mode, after the initial word is output, subsequent
active edges of CLK increment the internal address counter. Should be at
V
IL
or V
IH
while in asynchronous mode.
(Common)
AVD#
Address Valid input.
Indicates to device that the valid address is present on the address inputs.
(Flash)
F-RST#
Hardware reset input.
F-WP#
Hardware write protect input.
At V
, disables program and erase functions in the four outermost sectors.
Should be at V
IH
for all other conditions.
F-ACC
Accelerated input.
At V
, accelerates programming; automatically places device in unlock
bypass mode. At V
, disables all program and erase functions. Should be
at V
IH
for all other conditions.
R-CE#
Chip-enable input for pSRAM
F1-CE#
Chip-enable input for Code Flash.
Asynchronous relative to
CLK for Burst Mode.
F2-CE#
Chip-enable input for Data Flash 1.
F2-CE#
Chip-enable input for Data Flash 2.
R-MRS#
Control Register Enable.
(pSRAM – RAM Type 4 only)
F-V
CC
Flash 1.8 Volt-only single power supply.
R-V
CC
pSRAM Power Supply.
R-UB#
Upper Byte Control.
(pSRAM)
R-LB#
Lower Byte Control .
Table 3.2 ORNAND Flash Input/Output Descriptions
Symbol
Description
N-PRE
ORNAND Power-On Read Enable. Tie to V
SS
on customer board if not used.
N-ALE
ORNAND Address Latch Enable
N-CLE
ORNAND Command Latch Enable
N-CE#
ORNAND Chip-enable
N-WP#
ORNAND Write-protect
N-WE#
ORNAND Write-enable
N-RE#
ORNAND Read-enable
N-RY/BY#
ORNAND Ready-Busy—this is shared with NOR RDY
N-I/O0-N-I/O15
ORNAND I/O signals (I/O0-I/O7 for x8 bus width)
N-V
CC
ORNAND Power supply
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