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參數(shù)資料
| 型號： | S75WS256NDFBAWLH2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA84 |
| 封裝： | 9 X 12 MM, 1.40 MM HEIGHT, FBGA-84 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 123K |
| 代理商： | S75WS256NDFBAWLH2 |
4
S73WS-P based MCP Products
S73WS-P_00_A0 March 16, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
3.2
NOR Flash and DRAM Input/Output Descriptions
Amax-A0
=
Address inputs, shared between NOR Flash and DRAM
DQ15-DQ0
=
Data input/output, shared between NOR Flash and DRAM
F-CE#
=
NOR Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode.
F-OE#
=
NOR Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
F-WE#
=
NOR Flash Write Enable input.
F-V
CC
F-V
CCQ
=
NOR Flash device power supply (1.7 V - 1.95V).
=
Input/Output Buffer power supply.
V
SS
=
Ground
RFU
=
Reserved for Future Use
F-RDY
=
Flash ready output. Indicates the status of the Burst read. VOL = data valid.
F-CLK
=
NOR Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input
and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK
increment the internal address counter. CLK should remain low during asynchronous access.
F-AVD#
=
NOR Flash Address Valid input. Indicates to device that the valid address is present on the address
inputs.
VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be
latched on rising edge of CLK.
VIH= device ignores address inputs
F-RST#
=
NOR Flash hardware reset input. VIL= device resets and returns to reading array data
F-WP#
=
NOR Flash hardware write protect input. VIL = disables program and erase functions in the four
outermost sectors.
F-ACC
=
NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
D-CE#
=
SDRAM Chip Select
D-CKE
=
SDRAM Clock Enable
D-BA1-BA0
=
SDRAM Bank Select
D-RAS#
=
SDRAM Row Address Strobe
D-CAS#
=
SDRAM Column Address Strobe
D-DM1-D-DM0
=
SDRAM Data Input/Output Mask
D-WE#
=
SDRAM Write Enable input
D-V
SS
=
SDRAM Ground
D-V
SSQ
D-V
CCQ
=
SDRAM Input/Output Buffer ground
=
SDRAM Input/Output Buffer power supply
D-V
CC
=
SDRAM device power supply
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