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| 型號： | S71GL064A80BFW0B2 |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM |
| 文件頁數(shù)： | 84/102頁 |
| 文件大?。?/td> | 1606K |
| 代理商： | S71GL064A80BFW0B2 |
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84
S71GL032A Based MCPs
S71GL032A_00_A0 March 31, 2005
A d v a n c e I n f o r m a t i o n
Table 26. Switching Characteristics
Notes:
1.
Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V
CC(typ.)
/2, input pulse levels of
0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
and 30 pF load capacitance.
t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
2.
3.
High-Z and Low-Z parameters are characterized and are not 100% tested.
4.
To achieve 55-ns performance, the read access should be CE# controlled. In this case t
ACE
is the critical parameter and t
SK
is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
5.
The internal write time of the memory is defined by the overlap of WE#, CE#1 = V
IL
, CE2 = V
IH
, B
HE
and/or B
LE
= V
IL
. All
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
Parameter
Description
Min
Max
Unit
Read Cycle
t
RC
Read Cycle Time
70
ns
t
AA
Address to Data Valid
70
t
OHA
Data Hold from Address Change
10
t
ACE
CE#1 Low and CE2 High to Data Valid
70
t
DOE
OE# Low to Data Valid
35
t
LZOE
OE# Low to Low Z (note 2, 3)
5
t
HZOE
OE# High to High Z (note 2, 3)
25
t
LZCE
CE#1 Low and CE2 High to Low Z (note 2, 3)
5
t
HZCE
CE#1 High and CE2 Low to High Z (note 2, 3)
25
t
DBE
BHE# / BLE# Low to Data Valid
70
t
LZBE
BHE# / BLE# Low to Low Z (note 2, 3)
5
t
HZBE
BHE# / BLE# High to High Z (note 2, 3)
25
t
SK
(note 4)
Address Skew
10
W rite Cycle ( note 5)
t
WC
Write Cycle Time
70
ns
t
SCE
CE#1 Low an CE2 High to Write End
55
t
AW
Address Set-Up to Write End
55
t
HA
Address Hold from Write End
0
t
SA
Address Set-Up to Write Start
0
t
PWE
WE# Pulse Width
55
t
BW
BLE# / BHE# LOW to Write End
55
t
SD
Data Set-up to Write End
25
t
HD
Data Hold from Write End
0
t
HZWE
WE# Low to High Z (note 2, 3)
25
t
LZWE
WE# High to Low Z (note 2, 3)
5
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