參數(shù)資料
型號(hào)： S524LB0XB1
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 32K/64K-bit Serial EEPROM
中文描述： 32K/64K-bit串行EEPROM
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 145K
代理商： S524LB0XB1
DATA SHEET
S524LB0D91/B0DB1 SERIAL EEPROM
7-5
FUNCTION DESCRIPTION
I
2
C-BUS INTERFACE
The S524LB0D91/B0DB1 supports the I
2
C-bus serial interface data transmission protocol. The two-wire bus
consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected
to V
CC
by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions,
controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524LB0D91/B0DB1 devices can be
connected to the same I
2
C-bus as slaves (see Figure 7-6). Both the master and slaves can operate as a
transmitter or a receiver, but the master device determines which bus operating mode would be active.
SDA
Bus Master
(Transmitter/
Receiver)
MCU
S524LB0D91/
B0XB1
Tx/Rx
A0 A1 A2
Slave 1
To V
CC
or V
SS
S524LB0D91/
B0XB1
Tx/Rx
A0 A1 A2
Slave 2
To V
CC
or V
SS
S524LB0D91/
B0XB1
Tx/Rx
A0 A1 A2
Slave 3
To V
CC
or V
SS
S524LB0D91/
B0XB1
Tx/Rx
A0 A1 A2
Slave 8
To V
CC
or V
SS
R
V
CC
R
V
CC
SCL
Figure 7-6. Typical Configuration
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