參數(shù)資料
型號(hào): S4406
廠商: Applied Micro Circuits Corp.
英文描述: 12-Output BiCMOS PLL Clock Generator(能產(chǎn)生12個(gè)時(shí)鐘輸出的BiCMOS鎖相環(huán)時(shí)鐘發(fā)生器)
中文描述: 12路輸出的BiCMOS PLL時(shí)鐘發(fā)生器(能產(chǎn)生12個(gè)時(shí)鐘輸出的BiCMOS工藝鎖相環(huán)時(shí)鐘發(fā)生器)
文件頁數(shù): 4/8頁
文件大?。?/td> 106K
代理商: S4406
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 4
PIN DESCRIPTIONS
Input Signals
REFCLK.
Frequency reference supplied by the user
that, along with the output tied to the FBCLK input,
determines the frequency of the outputs. Also re-
places the VCO output when TSTEN is high (after
first divide-by-two stage in divider phase control
logic). See TSTEN.
FBCLK.
Feedback clock that, along with the REFCLK
input, determines the frequency of the outputs. One
output is selected to feed back to this input.
TSTEN.
Active High. Allows REFCLK to drive the
divider phase adjust circuitry, after the first divide-by-
two stage. Also, when brought High, generates an
internal Reset pulse that initializes the internal
counter flip-flops to zero.
xMS2,1,0.
Mode selection inputs that allow selection
of the phase and frequency relationship of each of
the four banks of three clock outputs. The “x” repre-
sents the output group number (0–3). Refer to Table
1 for mode selection options.
Output Signals
FILTER.
A tap between the analog output of the
phase detector and the VCO input. Allows a simple
external filter (a single resistor and one capacitor) to
be included in the PLL.
xFOUT0–2.
Clock signal outputs. Refer to Table 1
and Figure 4 for a description of output options.
S4406
PIN DESCRIPTIONS
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