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參數(shù)資料
| 型號： | S4406 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | 12-Output BiCMOS PLL Clock Generator(能產(chǎn)生12個(gè)時(shí)鐘輸出的BiCMOS鎖相環(huán)時(shí)鐘發(fā)生器) |
| 中文描述： | 12路輸出的BiCMOS PLL時(shí)鐘發(fā)生器（能產(chǎn)生12個(gè)時(shí)鐘輸出的BiCMOS工藝鎖相環(huán)時(shí)鐘發(fā)生器） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 106K |
| 代理商： | S4406 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 2
S4406
FUNCTIONAL DESCRIPTION
xMS2,1,0
MODE DESCRIPTION
xFOUT0,1,2
000
Disabled.
Logical Hi
001
All three outputs at the
fundamental output freq-
uency, but early by a
minimum phase delay.
f – t
010
All three outputs at half
the fundamental output
frequency and inverted.
I
/2
011
All three outputs at the
fundamental output freq-
uency and inverted.
I
100
All three outputs at half
the fundamental output
frequency, but delayed
by a minimum phase delay.
f/2 + t
101
All three outputs at the
fundamental output freq-
uency, but delayed by a
minimum phase delay.
f + t
110
All three outputs at half
the fundamental output
frequency.
f/2
111
All three outputs at the
fundamental output
frequency.
f
Table 1. Mode Selection Options
Note: If f is fed back, the fundamental frequency is equal to REFCLK.
If f/2 is fed back, the fundamental frequency is twice REFCLK.
110, and the third group (2MS2,1,0) to 101. In this
configuration, one of the 33-MHz outputs should be
fed back to the FBCLK input. This example makes
use of only three of the four output banks, leaving the
fourth available for any other clock signals needed.
Filter
FILTER is the analog signal from the phase detector
going into the VCO. This pin is provided so a simple
external filter (a single capacitor and resistor) can be
included in the phase locked loop of the clock gen-
erator. See Figure 3.
Phase Delay
The minimum phase delay between xFOUT0–2 sig-
nals is a function of the VCO frequency. The VCO
frequency can be determined by multiplying the fun-
damental output frequency by four, or half the funda-
mental frequency by eight. The minimum phase
delay is equal to the period of the VCO frequency: t =
1/(VCO freq). Since the VCO can operate in the 160-
MHz to 266-MHz range, the range of minimum phase
delay values is 6.25 ns to 3.75 ns (See Table 2).
FUNCTIONAL DESCRIPTION
The 12 xFOUT0–2 outputs are the main TTL output
clocks that the generator supplies. The mode selec-
tion choices are shown in Table 1 and waveform defi-
nitions are given in Figure 2. The “x” represents the
output group number (1–4). The frequency of these
outputs is determined by the REFCLK clock fre-
quency and the output clock that is tied to the FBCLK
input (xFOUT0–2 can be equal to REFCLK, half of
REFCLK, or twice the frequency of REFCLK).
Example:
In order to meet bus timing specifications for a typical
system, designers may need three outputs at 66 MHz
for the system clock and processor, a 33-MHz output
for the cache controller, and a 33-MHz delayed out-
put for a memory management unit. This system re-
quirement can be met using the S4406 by setting the
mode select pins for the first group of outputs
(0MS2,1,0) to 111, the second group (1MS2,1,0) to
Figure 2. Waveform Definitions
Figure 3. External PLL Filter
A +5V
.1 μF
1.5k
43
42
S4406
A VCC
FILTER
f
f/2
f + t
f – t
REFCLK
Table
entry
Waveform
I
I
/2
–t 0 t
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