- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98069 > S3P72M9-QA 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP128 PDF資料下載
參數(shù)資料
| 型號(hào)： | S3P72M9-QA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, QFP-128 |
| 文件頁(yè)數(shù)： | 19/265頁(yè) |
| 文件大?。?/td> | 1133K |
| 代理商： | S3P72M9-QA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)
INTERRUPTS
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
7-2
Vectored Interrupts
Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program
software. A vectored interrupt is generated when the following flags and register settings, corresponding to the
specific interrupt (INTn) are set to logic one:
— Interrupt enable flag (IEx)
— Interrupt master enable flag (IME)
— Interrupt request flag (IRQx)
— Interrupt status flags (IS0, IS1)
— Interrupt priority register (IPR)
If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is
loaded into the program counter and the program starts executing the service routine from this address.
EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM
during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction.
The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the
main routine, as well as during service routines. Any changes that are made to enable flag values during a
service routine are not stored in the vector address.
When an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the program
status word (PSW), and the enable flag values for the interrupt is fetched from the respective vector address.
Then, if necessary, you can modify the enable flags during the interrupt service routine. When the interrupt
service routine is returned to the main routine by the IRET instruction, the original values saved in the stack are
restored and the main program continues program execution with these values.
Software-Generated Interrupts
To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the
interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met,
and the service routine can be initiated.
Multiple Interrupts
By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and
thereby process multiple interrupts simultaneously.
If more than four interrupts are being processed at one time, you can avoid possible loss of working register data
by using the PUSH RR instruction to save register contents to the stack before the service routines are executed
in the same register bank. When the routines have executed successfully, you can restore the register contents
from the stack to working memory using the POP instruction.
Power-Down Mode Release
An interrupt can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are
initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down
mode will be released by an interrupt request signal when the interrupt enable flag has been set. In such cases,
the interrupt routine will not be executed since IME = "0".
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S3C7414XX-AQ | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP42 |
| S3C7414XX-QZ | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| S3P7414XX-QZ | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| S3P7434XX-QZ | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP44 |
| S3C7538XX-SO | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3P72N4 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrange |
| S3P72N5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:single-chip CMOS microcontroller |
| S3P72P9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:SINGLE-CHIP MICROCONTROLLER HAS BEEN DESIGNED FOR HIGH PERFORMANCE USING |
| S3P72Q5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4?BIT CMOS MICROCONTROLLER USERS MANUAL |
| S3P7324 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。