
REGISTERS
S3FB42F
3-2
INDEX REGISTERS: IDH, IDL0 AND IDL1
IDH in concatenation with IDL0 (or IDL1) forms a 16-bit data memory address. Note that CalmRISC’s data memory
address space is 64K bytes (addressable by 16-bit addresses). Basically, IDH points to a page index and IDL0 (or
IDL1) corresponds to an offset of the page. Like GPR’s, the index registers are 2-way banked. There are 2 banks in
total, each of which has its own index registers, IDH, IDL0 and IDL1. The banks of index registers can be switched
by setting an appropriate value in SR0[2] (See SR0 for details). Normally, programmers can reserve an index register
pair, IDH and IDL0 (or IDL1), for software stack operations.
LINK REGISTERS: ILX, ILH AND ILL
The link registers are specially designed for link-and-branch instructions (See LNK and LRET instructions in the
instruction sections for details). When an LNK instruction is executed, the current PC[19:0] is saved into ILX, ILH
and ILL registers, i.e., PC[19:16] into ILX[3:0], PC[15:8] into ILH [7:0], and PC[7:0] into ILL[7:0], respectively. When
an LRET instruction is executed, the return PC value is recovered from ILX, ILH, and ILL, i.e., ILX[3:0] into PC[19:16],
ILH[7:0] into PC[15:8] and ILL[7:0] into PC[7:0], respectively. These registers are used to access program memory
by LDC/LDC+ instructions. When an LDC or LDC+ instruction is executed, the (code) data residing at the program
address specified by ILX:ILH:ILL will be read into TBH:TBL. LDC+ also increments ILL after accessing the program
memory.
There is a special core input pin signal, nP64KW, which is reserved for indicating that the program memory address
space is only 64 K word. By grounding the signal pin to zero, the upper 4 bits of PC, PC[19:16], is deactivated and
therefore the upper 4 bits , PA[19:16], of the program memory address signals from CalmRISC core are also
deactivated. By doing so, power consumption due to manipulating the upper 4 bits of PC can be totally eliminated
(See the core pin description section for details). From the programmer’s standpoint, when nP64KW is tied to the
ground level, then PC[19:16] is not saved into ILX for LNK instructions and ILX is not read back into PC[19:16] for
LRET instructions. Therefore, ILX is totally unused in LNK and LRET instructions when nP64KW = 0.