
MAC2424
S3FB42F
25-28
M16
– Bit 11
This bit defines current operation mode of the MAC2424 DSP coprocessor. If this bit is set, it indicates the current
operation mode is 16-bit mode, and data registers and flags are configured to 16-bit mode. If this bit is clear (reset
state), the MAC2424 operates on normal 24-bit mode. The M16bit is only affected when MSR0 register write
operation or "ER/ES M16" instruction is used.
XSD
– Bit 10
This bit defines current bank of index register for index register read or write operation, and the length of index value
for address modification. When this bit is set, the current bank of index register is SD0E and SD3E instead of SD0
and SD3, respectively. When clear, the current index registers are SD0 and SD3. (reset state) During indirect
addressing mode, pointer register RPi is post-modified by index register value. If XSD is set, the width of index value
becomes to 8-bit by concatenating extension index register and normal index register. If clear, the normal 4-bit index
value is applied. The XSD bit can be modified by writing to MSR0 register or "ER/ES XSD" instruction. The XSD bit is
cleared by a processor reset.
OPB/OPA
– Bit 9/Bit 8
The OPB/OPA bit indicates that saturation arithmetic in the ARU is provided or not when overflow is occurred during
data move or arithmetic operation. The overflow protection can be applied to A and B register respectively. If this bit
is set, the saturation logic will substitute a limited value having maximum magnitude and the same sign as the
source Ai register during overflow. If clear, no saturation is performed, and overflow is not protected by the MAC2424.
The OPA/OPB bit can be modified by writing to MSR0 register or "ER/ES OPA/OPB" instruction. The OPA/OPB bit
is cleared by a processor reset.
VS
– Bit 6
The VS bit is a overflow flag for BEU(Barrel Shifter and Exponent Unit). This bit is set if arithmetic overflow is
occurred during shift operation or exponent evaluation on BEU registers. When the instructions which performs BEU
operation writes this bit as a overflow flag instead of VA or VB bit. The VS bit indicates that the result of a shift
operation can not be represented in 16-bit SR register, or the source value of an exponent operation is all zero or all
one. The VS bit can be modified by writing to MSR0 register instruction.