
MAC2424
S3FB42F
25-24
Each space is divided into 3 16 Kbyte XE/XH/XL or YE/YH/YL region when 24-bit data is needed, or 2 16 Kbyte
XH/XL or YH/YL region when 16-bit data is needed, respectively. Each space can contain RAM or ROM, and can be
off-chip or on-chip. In the X data space, the lower 128 byte locations are reserved for memory-mapped I/O. The
MAC2424 coprocessor can not access the I/O region. only host processor can access. The configuration of this
region depends on the specific chip configuration.
When 24-bit width data memory is used, the total memory space becomes to 96 Kbyte (16 Kbyte * 6). Because
CalmRISC can only access 64 Kbyte memory space, the extended memory regions (XE and YE) are shadowed in
the high address memory region (XH and YH). So, CalmRISC can access XH/XL pair or XE/XL pair in a time. The
selection of shadowed region can be accomplished with "SYS #imm" instruction in CalmRISC. (Refer to each
evaluation chip specification)
ARITHMETIC UNIT
The Arithmetic Unit (ARU) performs all arithmetic operations on data operands. It is a 24-bit, single cycle, non-
pipelined arithmetic unit. The MAC2424 is a coprocessor of CalmRISC microcontroller. So, all the logical operation
and other bit manipulation operations can be performed in CalmRISC. Thus, the MAC2424 has not logical units and
bit manipulation units at all.
The ARU receives one operand from Ai(A or B) register, and another operand from either the MSB part of MA
register, the XB bus, or from Ai. Operations between the two Ai register are possible. The source and destination Ai
register of an ARU instruction is always the same. The XB bus input is used for transferring one of the MAC2424
register content, an immediate operand, or the content of a data memory location, addressed in direct addressing
mode or in indirect addressing mode as a source operand. The flags in the MSR0 register are affected as a result of
the ARU output. In most of the instructions where the ARU result is transferred to one of Ai registers, the flags
represent the Ai register status. The detailed block diagram of the Arithmetic Unit is shown in Figure 25-12.
24-bit Adder
XB[23:0]
A
B
Shifter
Saturation
MSR0
MSR2
EI Generation
Figure 25-12. Arithmetic Unit Block Diagram