
S3FB42F
MAC2424
25-25
The ARU can perform add, subtract, compare, several other arithmetic operations (such as increment, decrement,
negate, and absolute), and some arithmetic shift operations. It uses two's complement arithmetic.
A, B ACCUMULATORS
Each Ai (A or B) register is organized as a regular 24-bit register. The Ai accumulators can serve as the source
operand, as well as the destination operand of the ARU instructions. The Ai registers can be read or written though
the XB bus. In the 16-bit mode operation, Ai register is organized as a regular 16-bit register (bit 15 to bit 0) and 8-bit
extension guard bits. (bit 23 to bit 16) When the result of a 24-bit adder output crosses bit 15, it sets Vi(VA or VB)
bit of MSR0 register (A/B register Overflow flag). The extension guard bits offer protection against 16-bit overflows up
to 255 overflows or underflows. If the sign is lost beyond the MSB of the extension guard bits, the result is lost and
the value can not be recovered. There is no overflow indication at 24-bit boundary in 16-bit operation mode. In 24-bit
operation mode, when the result of a 24-bit adder output crosses bit 23, it sets Vi.
OVERFLOW PROTECTION IN A/B ACCUMULATORS
The Ai accumulator saturation is performed differently according to the current operation mode. In 24-bit operation
mode, the selected accumulator value is saturated during arithmetic operation which causes overflow, if overflow
protection bit (OPA or OPB bit in MSR0 register) is enabled. The limited values are 7FFFFFh (positive overflow), or
800000h (negative overflow). During accumulator register read through XB bus, the saturation is not occurred.
Contrary, in 16-bit operation mode, saturation is not occurred during arithmetic operation. The saturation is only
occurred during accumulator register read through XB bus, if overflow protection is enabled and overflow occurred
(OPA/OPB bit of MSR0 register is set, and VA/VB bit of MSR0 register is set). The saturated values are 007FFFh
(positive overflow) or FF8000h (negative overflow).
–
Saturation Condition at 24-bit mode : Arithmetic instruction & 24-bit Overflow & OPA/OPB
–
Saturation Condition at 16-bit mode : Read A/B & VA/VB & OPA/OPB
A/B
0
23
A/B
0
23
A/B
A/B Guard Region
A/B
15
16
A/B
mode24
mode16
Figure 25-13. Ai Accumulator Register Configuration