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參數(shù)資料
| 型號(hào)： | S3057 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH/ATM Transceiver(帶片上鎖相環(huán)的多速率SONET/SDH/ATM收發(fā)器) |
| 中文描述： | 多速率SONET / SDH / ATM的收發(fā)器（帶片上鎖相環(huán)的多速率的SONET / SDH / ATM的收發(fā)器） |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 238K |
| 代理商： | S3057 |
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S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
October 31, 2000 / Revision E
S3057 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3057 transceiver chip performs the serialization
stage in the processing of a transmit SONET STS-48/
STS-24/STS-12/STS-3/GBE data stream depending
on the data rate selected. It converts 16 bit parallel
data to bit serial format at 2488.32/1244.16/622.08/
155.52/1250 Mbps.
A high-frequency bit clock can be generated from a
155.52 MHz frequency reference by using an inte-
gral frequency synthesizer consisting of a
phase-locked loop circuit with a divider in the loop.
Diagnostic loopback (transmitter to receiver) and line
loopback (receiver to transmitter) is provided. See
Other Operating Modes.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock frequency locked to the input
Reference Clock (REFCLKP/N).
The REFCLKP/N input must be generated from a
crystal oscillator which has a frequency accuracy
that meets the value stated in Table 8 in order for
the TSCLK frequency to have the same accuracy
required for operation in a SONET system. Lower
accuracy crystal oscillators may be used in applica-
tions less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The Timing Generation function, seen in Figure 4,
provides a divide-by-16 version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[15:0] data from
the parallel input register to the serial shift register.
The PCLK output is a divide-by-16 rate version of
transmit serial clock (divide-by-16). PCLK is intended
for use as a divide-by-16 clock for upstream multi-
plexing and overhead processing circuits. Using
PCLK for upstream circuits will ensure a stable fre-
quency and phase relationship between the data
coming into and leaving the S3057 device.
The timing generator also produces a feedback ref-
erence clock to the clock synthesizer. A counter
divides the synthesized clock down to the same fre-
quency as the reference clock REFCLK. The PLL in
the clock synthesizer maintains the stability of the
synthesized clock by comparing the phase of the in-
ternal clock with that of the Reference Clock
(REFCLK).
Table 3. Reference Jitter Limits
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