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參數(shù)資料
| 型號(hào)： | S3057 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH/ATM Transceiver(帶片上鎖相環(huán)的多速率SONET/SDH/ATM收發(fā)器) |
| 中文描述： | 多速率SONET / SDH / ATM的收發(fā)器（帶片上鎖相環(huán)的多速率的SONET / SDH / ATM的收發(fā)器） |
| 文件頁(yè)數(shù)： | 3/26頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | S3057 |
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3
S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
October 31, 2000 / Revision E
Figure 3. STS–48/OC–48 Frame Format
S3057 OVERVIEW
The S3057 transceiver implements SONET/SDH se-
rialization/deserialization, and transmission
functions. The block diagram in Figure 4 shows the
basic operation of the chip. This chip can be used to
implement the front end of SONET equipment, which
consists primarily of the serial transmit interface and
the serial receive interface. The chip handles all the
functions of these two elements, including parallel-to-
serial and serial-to-parallel conversion, clock
generation, and system timing. The system timing
circuitry consists of management of the data stream
and clock distribution throughout the front end.
9
48 A1
Bytes
48 A2
Bytes
A1 A1
A1 A1
A2 A2
A2 A2
Transport Overhead 144 Columns
144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns
4176 x 9 = 37,584 bytes
125
μ
sec
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Table 2. Data Rate Select
The S3057 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Transmitter Operations:
1. 16-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Serial input
2. Serial-to-parallel conversion
3. 16-bit parallel output
Internal clocking and control functions are transpar-
ent to the user.
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Suggested Interface Devices
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