- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374665 > S3044 (APPLIEDMICRO INC) SONET/SDH/ATM OC-48 1：16 Receiver(帶片上高頻鎖相環(huán)的1：16 SONET/SDH接收器（集成SONET OC-48接口器件）) PDF資料下載
參數(shù)資料
| 型號： | S3044 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-48 1：16 Receiver(帶片上高頻鎖相環(huán)的1：16 SONET/SDH接收器（集成SONET OC-48接口器件）) |
| 中文描述： | MUX/DEMUX, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 439K |
| 代理商： | S3044 |
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
4
December 8, 2000 / Revision H
RECEIVER OPERATION
The S3044 receiver chip provides the first stage of
digital processing of a receive SONET STS-48 bit-
serial stream. It converts the bit-serial 2.488 Gbps
data stream into a 155.52 Mbyte/sec byte-serial data
format. A loopback mode is provided for diagnostic
loopback (transmitter to receiver). A Line Loopback
(receiver to transmitter) is also provided.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by one A2 byte. Framing
pattern detection is enabled and disabled by the
FRAMEN input. Detection is enabled by a rising edge
on OOF when FRAMEN is active. It is disabled when
a framing pattern is detected. When framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming data
stream (RSD or looped transmitter data). During this
time, the parallel data bus (POUT [15:0]) will not
contain valid data. The timing generator block takes
the located byte boundary and uses it to block the
incoming data stream into bytes for output on the
parallel output data bus (POUT[15:0]). The frame
boundary is reported on the frame pulse (FP) output
when any 32-bit pattern matching the framing pat-
tern is detected on the incoming data stream. When
framing pattern detection is disabled, the byte bound-
ary is frozen to the location found when detection
was previously enabled. Only framing patterns
aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-48
stream will generate the 32-bit framing pattern is ex-
tremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occur-
rence of the pattern, is expected to be less than the
required 250
μ
s, even for extremely high bit error
rates.
Serial to Parallel Converter
The Serial to Parallel Converter consists of three
16-bit registers. The first is a serial-in, parallel-out
shift register, which performs the serial to parallel
conversion. The second is an 16-bit internal holding
register, which transfers data from the serial to par-
allel register on byte boundaries as determined by
the frame and byte boundary detection block. On the
falling edge of the free running POCLK, the data in
the holding register is transferred to an output hold-
ing register which drives POUT[15:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output clock
and data from the transmitter (LSCLK and LSD) is
routed to the serial-to-parallel block in place of the
normal data stream (RSCLK and RSD).
Line Loopback
The Line Loopback circuitry consists of alternate
clock and data output drivers. When LLEB is active,
it enables the Line Loopback output data and clock
(LLD and LLCLK), and a receive-to-transmit
loopback can be established at the serial data rate.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S3045 | SONET/SDH OC-12 to OC-48 Mux/Demux(SONET/SDH多路轉(zhuǎn)換器/多路分解器) |
| S3050 | Multi-Rate SONET/SDH Clock Recovery Unit(多速率SONET/SDH時鐘恢復(fù)單元) |
| S3051 | 2.5 Gbps Limiting Amplifier(用于光纖接收的高增益寬帶寬的2.5 Gbps限幅放大器) |
| S3055 | SONET/SDH/ATM OC-48 16 Bit Transceiver with CDR(SONET/SDH 帶CDR的16位收發(fā)器（完全集成OC-48接口器件）) |
| S3056 | Multi-Rate SONET/SDH Clock Recovery Unit(多速率SONET/SDH時鐘恢復(fù)單元) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S30440 | 制造商:Microsemi Corporation 功能描述:400V 40A 2PIN DO-5 - Bulk |
| S3045 | 制造商:KODENSHI 制造商全稱:KODENSHI KOREA CORP. 功能描述:4CH BTL Motor Drive IC |
| S3045B | 制造商:AppliedMicro 功能描述: |
| S30460 | 制造商:Microsemi Corporation 功能描述:Diode 600V 40A 2-Pin DO-5 制造商:Microsemi Corporation 功能描述:600V 40A 2PIN DO-5 - Bulk |
| S30480 | 制造商:Microsemi Corporation 功能描述:800V 40A 2PIN DO-5 - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。