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參數(shù)資料
| 型號： | S3044 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-48 1：16 Receiver(帶片上高頻鎖相環(huán)的1：16 SONET/SDH接收器（集成SONET OC-48接口器件）) |
| 中文描述： | MUX/DEMUX, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 439K |
| 代理商： | S3044 |
15
S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
December 8, 2000 / Revision H
RECEIVER FRAMING
Figure 10 shows a typical reframe sequence in
which a byte realignment is made. The frame and
byte boundary detection is enabled by the rising
edge of OOF. Both boundaries are recognized upon
receipt of the first A2 byte. The third A2 byte is the
first data byte to be reported with the correct byte
alignment on the outgoing data bus (POUT[15:0]).
Concurrently, the frame pulse is set high for one
POCLK cycle.
The frame and byte boundary detection block is acti-
vated by the rising edge of OOF, and stays active until
the first FP pulse.
Figure 11 shows the frame and byte boundary detection
activation by a rising edge of OOF, and deactivated by
the first FP pulse.
Figure 12 shows the frame and byte boundary detec-
tion activation by a rising edge of OOF, and deacti-
vated by the FRAMEN input.
Figure 10. Frame and Byte Detection
1. Range of input to output delay can be 1.5 to 2.5 POCLK cycles.
A1
A1
A1
A2
A2
A2
A2
A2
Note 1
A1, A1
A1, A1
A1, A1
A2, A2
A2, A2
Invalid Data
Valid Data
RECOVERED
CLOCK/
REFCLK
OOF
SERDATI
POUT[15:0]
POCLK
FP
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