參數(shù)資料
型號(hào)： S3019
廠(chǎng)商： APPLIEDMICRO INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SONET/SDH/ATM OC-3/12 Transceiver W/CDR(SONET/SDH/ATM收發(fā)器(完全集成OC-3/12接口器件))
中文描述： TRANSCEIVER, PQFP80
封裝： 14 X 14 MM, PLASTIC, QFP-80
文件頁(yè)數(shù)： 7/22頁(yè)
文件大?。?/td> 437K
代理商： S3019
7
S3019
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
March 2, 2001 / Revision G
The probability that random data in an STS-3 or STS-
12 stream will generate the 48-bit framing pattern is
extremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occurrence
of the pattern, is expected to be less than the required
250
μ
s, even for extremely high bit error rates.
Once down-stream overhead circuitry has verified
that frame and byte synchronization are correct, the
OOF input can be set low to disable the frame
search process from trying to synchronize to a mimic
frame pattern
Serial-to-Parallel Converter
The Serial to Parallel Converter consists of three
8-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial-to-parallel con-
version clocked by the clock recovery block. The
second is an 8-bit internal holding register, which
transfers data from the serial-to-parallel register on
byte boundaries as determined by the frame and
byte boundary detection block. On the falling edge of
the free running POCLK, the data in the holding reg-
ister is transferred to an output holding register
which drives POUT[7:0].
The delay through the serial-to-parallel converter
can vary from 1.5 to 3.5 byte periods (12 to 28 serial
bit periods) measured from the first bit of an incom-
ing byte to the beginning of the parallel output of that
byte. The variation in the delay is dependent on the
alignment of the internal parallel load timing, which is
synchronized to the data byte boundaries, with respect
to the falling edge of POCLK, which is independent of
the byte boundaries. The advantage of this serial to
parallel converter is that POCLK is neither truncated
nor extended during reframe sequences.
(See Figures 13 through 15.)
Parity Calculation and Detection
The receiver section calculates odd parity for the
POUT[7:0] signals and provides the result at the
PAROUT pin. For example:
POUT[7:0] = 1001 1000; PAROUT = 1
POUT[7:0] = 1100 1001; PAROUT = 0
The transmitter performs parity error detection over
the PIN[7:0] data and the PARIN input. The result of
the detection is provided at the PARERR output.
Note that the PARIN should be calculated by the
same method as the receiver section PAROUT.
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is
low, a loopback from the transmitter to the receiver
at the serial data rate can be set up for diagnostic
purposes. The differential serial output data from the
transmitter is routed to the serial-to-parallel block in
place of the normal data stream (RSD). SDPECL
must be High for diagnostic loopback.
Line Loopback
The Line Loopback circuitry consists of alternate
clock and data output drivers. For the S3019, it se-
lects the source of the data and clock which is
output on TSD and TSCLK. When the Line
Loopback Enable input (LLEB) is high, it selects
data and clock from the Parallel to Serial Converter
block. When LLEB is Low and BYPASS is inactive,
the recovered clock is used to retime the incoming
data before driving the TSDP/N output. The
TSCLKP/N output will be driven by the recovered
clock. When LLEB is Low and BYPASS is active,
the RSCLKP/N input is used to retime the incoming
data before driving the RSDP/N input.
Serial Loop Timing
In Serial Loop Timing mode (SLPTIME), the clock
synthesizer PLL of the S3019 is bypassed, and the
timing of the entire transmitter section is controlled
by the receive serial clock. This mode is entered
using the SLPTIME input.
In this mode the REFCLKP/N input is not used, and
the MODE[1:0] inputs are ignored for all transmit
functions. It should be carefully noted that the inter-
nal PLL continues to operate in this mode, and
continues as the source for the (19, 38, 51)
MHZCLK, and if these signals are being used (e.g.
as the reference for an external clock recovery de-
vice), the REFCLKP/N and MODE[1:0] inputs must
be properly driven.
相關(guān)PDF資料
PDF描述
S3023 SONET/SDH/ATM Clock Recovery Unit(SONET/SDH/ATM時(shí)鐘恢復(fù)單元)
S3024 SONET/SDH/ATM Clock Recovery Unit(帶片上鎖相環(huán)的SONET/SDH/ATM時(shí)鐘恢復(fù)單元)
S3025 SONET/SDH/ATM Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH/ATM時(shí)鐘恢復(fù)單元)
S3026 SONET/SDH/ATM Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH/ATM時(shí)鐘恢復(fù)單元)
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