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參數(shù)資料
| 型號(hào)： | S3019 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(SONET/SDH/ATM收發(fā)器(完全集成OC-3/12接口器件)) |
| 中文描述： | TRANSCEIVER, PQFP80 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 5/22頁(yè) |
| 文件大?。?/td> | 437K |
| 代理商： | S3019 |
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S3019
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
March 2, 2001 / Revision G
RECEIVER OPERATION
The S3019 transceiver chip provides the first stage
of digital processing of a receive SONET STS-3 or
STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbps data stream into a 19.44 or
77.76 Mbps 8-bit parallel data format.
Clock recovery is performed on the incoming
scrambled NRZ data stream. A 19.44 or 77.76 MHz
reference clock is required for phase locked loop
start-up and proper operation under loss of signal
conditions. An integral prescaler and phase locked
loop circuit is used to multiply this reference to the
nominal bit rate.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver).
S3019 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3019 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3
or STS-12-bit serial data stream. It converts the 8-bit
parallel 19.44 or 77.76 Mbps data stream into bit
serial format at 155.52 or 622.08 Mbps.
A high-frequency bit clock can be generated from a
19.44 or 77.76 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.
Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes on page 7.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock phase synchronized with the input
reference clock (REFCLKP/N or TTLREF).
The REFCLKP/N or TTLREF input must be gener-
ated from a crystal oscillator which has a frequency
accuracy that meets the value stated in Table 9 in
order for the TSCLK frequency to have the same
accuracy required for operation in a SONET system.
Lower accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N or TTLREF input, a loop
filter which converts the phase detector output into a
smooth DC voltage, and a VCO, whose frequency is
varied by this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Table 3. Reference Frequency Options
E
D
O
M
]
C
N
E
U
Q
E
R
F
0
0
z
H
M
4
4
1
Timing Generation
The timing generation function, seen in Figure 4,
provides a byte rate version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[7:0] data from
the parallel input register to the serial shift register.
The PCLK output is a byte rate version of transmit
serial clock at 19.44 or 77.76 MHz. PCLK is intended
for use as a byte speed clock for upstream multiplex-
ing and overhead processing circuits. Using PCLK
for upstream circuits will ensure a stable frequency
and phase relationship between the data coming into
and leaving the S3019 device.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.
The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed relationship
to PCLK. If PICLK is tied to PCLK, the PIN[7:0] data
latched into the parallel register will meet the timing
specifications with respect to the load signal. If PICLK
is not tied to PCLK, the delay must meet the timing
requirements shown in Table 14.
Table 4. Reference Jitter Limits
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c
n
e
u
q
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r
F
d
n
a
B
e
c
n
e
r
r
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R
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m
c
u
m
o
C
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a
M
k
g
n
r
d
o
e
p
M
O
e
z
H
M
5
o
z
H
k
2
1
s
m
r
s
p
4
1
2
1
–
S
T
S
z
H
M
1
o
z
H
k
2
1
s
m
r
s
p
6
5
3
–
S
T
S
* Only valid in SLP mode.
K
C
O
Y
L
C
E
C
N
E
R
E
F
E
R
G
N
I
A
D
O
S
T
R
E
M
S
P
O
E
2
1
1
0
z
H
M
8
8
3
2
1
S
T
S
0
1
z
H
M
4
8
5
2
1
S
T
S
1
1
z
H
M
6
7
7
2
1
S
T
S
C
N
0
z
H
M
4
4
1
3
S
T
S
C
N
1
z
H
M
8
8
3
3
S
T
S
0
C
N
z
H
M
4
8
5
3
S
T
S
1
C
N
z
H
M
6
7
7
*
3
S
T
S
C
N
C
N
d
e
w
o
t
N
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