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參數(shù)資料
| 型號(hào)： | S3019 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(SONET/SDH/ATM收發(fā)器(完全集成OC-3/12接口器件)) |
| 中文描述： | TRANSCEIVER, PQFP80 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 1/22頁(yè) |
| 文件大?。?/td> | 437K |
| 代理商： | S3019 |
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S3019
S3019
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
March 2, 2001 / Revision G
DEVICE
SPECIFICATION
FEATURES
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLLs for clock
generation and clock recovery
Supports 155.52 Mbps (OC-3) and 622.08
Mbps (OC-12)
Selectable reference frequencies of 19.44,
38.88, 51.84 or 77.76 MHz
Interface to both LVPECL and TTL logic
Simple interface with 3.3 V or 5 V Optical
modules
Directly compatible with 3.3 V or 5 V network
interface devices
8-bit TTL data path
Compact 14 mm 80 PQFP package
Diagnostic loopback mode
Lock detect
Low jitter LVPECL interface
Single 3.3 V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
GENERAL DESCRIPTION
The S3019 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET OC-12
(622.08 Mbit/s) and OC-3 (155.52 Mbps) interface de-
vice. The chip performs all necessary serial-to-parallel
and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure
1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3019
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3019 also per-
forms SONET/SDH frame detection. The chip can be
used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-
ence clock, in support of existing system clocking
schemes.
The low jitter LVPECL interface guarantees compliance
with the bit-error rate requirements of the Bellcore
and ITU-T standards. The S3019 is packaged in a
14 mm 80 PQFP, offering designers a small package
outline.
S3019
SONET/SDH
Transceiver
Network
Interface
Processor
Network
Interface
Processor
S3019
SONET/SDH
Transceiver
OTX
ORX
OTX
ORX
8
8
8
8
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