參數(shù)資料
型號(hào)： S29PL127J70BFI000
廠商： SPANSION LLC
元件分類： PROM
英文描述： 8M X 16 FLASH 3V PROM, 70 ns, PBGA80
封裝： 11 X 8 MM, LEAD FREE, FBGA-80
文件頁(yè)數(shù)： 85/97頁(yè)
文件大?。?/td> 3042K
代理商： S29PL127J70BFI000
86
S29PL-J
S29PL-J_00_A10 September 7, 2007
Data
Sheet
(Adv an ce
Inf o r m a t io n)
Note
This parameter is defined for CE1#/CE2# recover time for read/read, program/read, and read/program operations. Program/program operation are not allowed and
only a single program operation is allowed at one time.
Figure 21.4 Timing Diagram for Alternating Between CE1# and CE2# Control
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals
assume checkerboard pattern. All values are subject to change.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 15.1
on page 64 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
Table 21.3 CE1#/CE2# Timing (S29PL129J only)
Parameter
Description
All Speed Options
Unit
JEDEC
Std
tCCR
CE1#/CE2# Recover Time (See Note)
Min
0
ns
Table 21.4 Erase And Programming Performance
Parameter
Max
Unit
Comments
Sector Erase Time
0.5
2
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
PL127J/129J
135
216
sec
PL064J
71
113.6
sec
PL032J
39
62.4
sec
Word Program Time
6
100
s
Excludes system level
overhead (Note 5)
Accelerated Word Program Time
4
60
s
Chip Program Time
PL127J/129J
50.4
200
sec
PL064J
25.2
50.4
sec
PL032J
12.6
25.2
sec
CE1#
tCCR
CE2#
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