參數(shù)資料
型號: S29PL127J70BFI000
廠商: SPANSION LLC
元件分類: PROM
英文描述: 8M X 16 FLASH 3V PROM, 70 ns, PBGA80
封裝: 11 X 8 MM, LEAD FREE, FBGA-80
文件頁數(shù): 64/97頁
文件大?。?/td> 3042K
代理商: S29PL127J70BFI000
September 7, 2007 S29PL-J_00_A10
S29PL-J
67
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
Figure 16.1 Data# Polling Algorithm
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being
erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
16.2
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one
of the banks is in the erase-suspend-read mode.
Table 16.1 on page 70 shows the outputs for RY/BY#.
16.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 400 s, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
DQ7 = Data?
Yes
No
DQ5 = 1?
No
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
相關(guān)PDF資料
PDF描述
S29XS064R0PBHW010 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
S2C3R-1-12-H 4000 MHz - 12000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2 dB INSERTION LOSS
S2C5R-1-12-RC 4000 MHz - 18000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2.8 dB INSERTION LOSS
S2H3R-1H 10 MHz - 1000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 1.2 dB INSERTION LOSS
S2L1R-RC 1000 MHz - 2000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 0.9 dB INSERTION LOSS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29PL127J70TAI130 制造商:Spansion 功能描述: 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays
S29PL127J70TFI130 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Trays
S29PL127J70TFI131 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Rail/Tube
S29PL127J70TFI132 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Tape and Reel
S29PL127J70TFI133 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 70NS 56TSOP - Tape and Reel