參數(shù)資料
型號(hào)： S29NS128J0PBFW002
廠商： SPANSION LLC
元件分類： PROM
英文描述： 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述： 8M X 16 FLASH 1.8V PROM, 65 ns, PBGA48
封裝： 10 X 11 MM, LEAD FREE, FBGA-48
文件頁(yè)數(shù)： 53/85頁(yè)
文件大小： 799K
代理商： S29NS128J0PBFW002
March 22, 2006 S29NS-J_00_A10
S29NS-J
49
D a t a S h e e t
Table 19. DQ6 and DQ2 Indications
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least
twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the system would com-
pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset command to
return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through suc-
cessive read cycles, determining the status as described in the previous paragraph. Alternatively,
it may choose to perform other system tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status of the operation.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was
not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was
previously programmed to “0.”
Only an erase operation can change a “ 0” back to a “ 1.”
Under this condition, the device halts the operation, and when the timing limit has been exceeded,
DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return to the read
mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program
mode).
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
actively erasing,
at an address within a sector selected
for erasure,
toggles,
also toggles.
at an address within sectors
not
selected for erasure,
toggles,
does not toggle.
erase suspended,
at an address within a sector selected
for erasure,
does not toggle,
toggles.
at an address within sectors
not
selected for erasure,
returns array data,
returns array data. The system can read from
any sector not selected for erasure.
programming in
erase suspend
at any address,
toggles,
is not applicable.
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