
March 22, 2006  S29NS-J_00_A10
S29NS-J
39
D a t a  S h e e t
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, 
and are then followed by the address of the sector to be erased, and the sector erase command. 
Table 18
 shows the address and data requirements for the sector erase command sequence.
The device does 
not
 require the system to preprogram prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the entire memory for an all zero data pattern prior to 
electrical erase. The system is not required to provide any controls or timings during these 
operations. 
After the command sequence is written, a sector erase time-out of no less than t
SEA
 (sector erase 
accept) occurs. During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any sequence, and the 
number of sectors may be from one sector to all sectors. The time between these additional cycles 
must be less than t
SEA
, otherwise erasure may begin. Any sector erase address and command 
following the exceeded time-out may or may not be accepted. It is recommended that processor 
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can 
be re-enabled after the last Sector Erase command is written. 
Any command other than Sector 
Erase or Erase Suspend during the time-out period resets that bank to the read mode. 
The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section 
on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in 
the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and ad-
dresses are no longer latched. Note that while the Embedded Erase operation is in progress, the 
system can read data from the non-erasing bank. The system can determine the status of the 
erase operation by reading DQ7 or DQ6/ DQ2 in the erasing bank. Refer to the 
Write Operation 
Status
 section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other 
commands are ignored. However, note that a 
hardw are reset 
immediately
terminates the erase 
operation. If that occurs, the sector erase command sequence should be reinitiated once that 
bank has returned to reading array data, to ensure data integrity.
Figure 2
 illustrates the algorithm for the erase operation. Refer to the 
Erase/Program Operations
table in the AC Characteristics section for parameters, and 
Figure 16
 section for timing diagrams.
Accelerated Sector Group Erase
Under certain conditions, the device can erase sectors in parallel. This method of erasing sectors 
is faster than the standard sector erase command sequence. 
Table 14
 lists the sector erase 
groups. 
The accelerated sector group erase function must not be used more than 100 times per 
sector. 
In addition, accelerated sector group erase should be performed at room temperature 
(30 + /- 10
°
C).