- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365401 > S29NS128J0PBFW002 (SPANSION LLC) 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories PDF資料下載
參數(shù)資料
| 型號： | S29NS128J0PBFW002 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 65 ns, PBGA48 |
| 封裝： | 10 X 11 MM, LEAD FREE, FBGA-48 |
| 文件頁數(shù)： | 22/85頁 |
| 文件大?。?/td> | 799K |
| 代理商： | S29NS128J0PBFW002 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
18
S29NS-J
S29NS-J_00_A10 March 22, 2006
D a t a S h e e t
The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at
V
CC
± 0.2 V. The device requires standard access time (t
CE
) for read access when the device is in
either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
I
CC3
in the
DC Characteristics
table represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enters this mode when addresses remain stable for t
ACC
+ 60 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always
available to the system. I
CC4
in the
DC Characteristics
table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of t
RP
, the device immediately terminates any
operation in progress, tristates all outputs, and ignores all read/write commands for the duration
of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
SS
± 0.2 V, the
device draws CMOS standby current (I
CC4
). If RESET# is held at V
IL
but not within V
SS
± 0.2 V, the
standby current will be greater.
RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the device requires a time of t
READYW
(during Embedded Algorithms) before the device is ready to read data again. If RESET# is as-
serted when a program or erase operation is not executing, the reset operation is completed
within a time of t
READY
(not during Embedded Algorithms). The system can read data t
RH
after
RESET# returns to V
IH
.
Refer to the
AC Characteristics
tables for RESET# parameters and to 14 for the timing diagram.
V
CC
Pow er-up and Pow er-dow n Sequencing
The device imposes no restrictions on V
CC
power-up or power-down sequencing. Asserting RE-
SET# to V
IL
is required during the entire V
CC
power sequence until the respective supplies reach
their operating voltages. Once V
CC
attains its operating voltage, de-assertion of RESET# to V
IH
is
permitted.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The outputs are placed in the
high impedance state.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes (refer to
Table 18
for command definitions).
The device offers three types of data protection at the sector level:
相關PDF資料 |
PDF描述 |
|---|---|
| S29NS128J0PBFW003 | 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW00 | 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW000 | 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW002 | 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW003 | 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS128J0PBFW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
| S29NS128J0PBJW003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories |
發(fā)布緊急采購，3分鐘左右您將得到回復。