參數(shù)資料
型號(hào)： S29NS032J0PBFW002
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
中文描述： 2M X 16 FLASH 1.8V PROM, 65 ns, PBGA44
封裝： 7.70 X 6.20 MM, LEAD FREE, FBGA-44
文件頁(yè)數(shù)： 23/85頁(yè)
文件大?。?/td> 799K
代理商： S29NS032J0PBFW002
March 22, 2006 S29NS-J_00_A10
S29NS-J
19
D a t a S h e e t
The sector lock/unlock command sequence disables or re-enables both program and erase
operations in any sector.
When WP# is at V
IL
,
—SA257 and SA258 are locked (S29NS128J)
—SA129 and SA130 are locked (S29NS064J)
—SA65 and SA66 are locked (S29NS032J)
—SA33 and SA34 are locked (S29NS016J)
When A
cc
is at V
IL
, all sectors are locked.
WP# Boot Sector Protection
The WP# signal will be latched at a specific time in the embedded program or erase sequence. To
prevent a write to the top two sectors, WP# must be asserted (WP#= V
IL
) on the last write cycle
of the embedded sequence (i.e., 4th write cycle in embedded program, 6th write cycle in embed-
ded erase).
If using the Unlock Bypass feature: on the 2nd program cycle, after the Unlock Bypass command
is written, the WP# signal must be asserted on the 2nd cycle.
If selecting multiple sectors for erasure: The WP# protection status is latched only on the 6th
write cycle of the embedded sector erase command sequence when the first sector is selected. If
additional sectors are selected for erasure, they are subject to the WP# status that was latched
on the 6th write cycle of the command sequence.
The following hardware data protection measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
W rite I nhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during
V
CC
power-up and power-down. The command register and all internal program/erase circuits are
disabled, and the device resets to reading array data. Subsequent writes are ignored until V
CC
is
greater than V
LKO
. The system must provide the proper signals to the control inputs to prevent
unintentional writes when V
CC
is greater than V
LKO
.
W rite Pulse “ Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical I nhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate
a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
相關(guān)PDF資料
PDF描述
S29NS032J0PBFW003 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW00 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW000 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW002 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW003 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29NS032J0PBFW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW00 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW000 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW002 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
S29NS032J0PBJW003 制造商:SPANSION 制造商全稱:SPANSION 功能描述:110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories
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