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參數(shù)資料
| 型號： | S29NS-N |
| 廠商： | Spansion Inc. |
| 英文描述： | Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| 中文描述： | 同步讀/寫，復(fù)用，突發(fā)模式閃存 |
| 文件頁數(shù)： | 18/86頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | S29NS-N |
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16
S29NS-N MirrorBit Flash Family
S29NS-N_00_A12 June 13, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Table 8.6
through
Table 8.8
show the address/boundary crossing latency for variable wait state if a boundary
crossing occurs during initial access
The device will continue to output continuous, sequential burst data, wrapping around to address 000000h
after it reaches the highest addressable memory location, until the system asserts CE# high, RESET# low, or
AVD# low in conjunction with a new address. See
Table 8.1 on page 14
. The reset command does
not
terminate the burst read operation.
If the host system crosses a 128 word line boundary while reading in burst mode, and the device is not
programming or erasing, no additional latency will occur as described above. If the host system crosses the
bank boundary while the device is programming or erasing, the device will provide asynchronous read status
information. The clock will be ignored. After the host has completed status reads, or the device has completed
the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse.
Table 8.5
Address Latency for 2 Wait States
Word
0
2 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
3
D3
D4
D5
D6
D7
D8
D9
D10
D11
Table 8.6
Address/Boundary Crossing Latency for 7, 6, and 5 Wait States
Word
0
7, 6, and 5 ws
D0
D1
D2
D3
1 ws
D4
D5
D6
D7
1
D1
D2
D3
1 ws
1 ws
D4
D5
D6
D7
2
D2
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
3
D3
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
D7
Table 8.7
Address/Boundary Crossing Latency for 4 Wait States
Word
0
4 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
D2
D3
1 ws
1 ws
D4
D5
D6
D7
D8
3
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
Figure 8.1
Address/Boundary Crossing Latency for 3 Wait States
Word
0
3 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
1 ws
D4
D5
D6
D7
D8
D9
3
D3
1 ws
1 ws
D4
D5
D6
D7
D8
D9
Table 8.8
Address/Boundary Crossing Latency for 2 Wait States
Word
0
2 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
D2
D3
D4
D5
D6
D7
D8
D9
D10
3
D3
1 ws
D4
D5
D6
D7
D8
D9
D10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29NS-N_07 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory |
| S29NS-P | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:MirrorBit Flash Family |
| S29PL032J | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL032J55BAI120 | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 32Mbit 2M x 16bit 55ns 48-Pin FBGA Tray 制造商:Spansion 功能描述:FLASH PARALLEL - Trays |
| S29PL032J55BFI120 | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 32MBIT 2MX16 55NS 48FBGA - Trays |
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