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參數(shù)資料
| 型號： | S29CD016G0MFAN010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 64 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 24/81頁 |
| 文件大小： | 1276K |
| 代理商： | S29CD016G0MFAN010 |
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28
S29CD-G Flash Family
S29CD-G_00_B1 March 3, 2009
Data
Sheet
(Pre limin ar y)
12.11.3
RESET# Control in Linear Mode
The RESET# pin immediately halts the linear burst access when taken to VIL. The DQ data bus signal float.
Additionally, the Configuration Register contents are reset back to the default condition where the device is
placed in asynchronous access mode.
12.11.4
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the
OE# pin to VIH during a burst operation floats the data bus. However, the device continues to operate
internally as if the burst sequence continues until the linear burst is complete. The OE# pin does not halt the
burst sequence, this is accomplished by either taking CE# to VIH or re-issuing a new ADV# pulse. The DQ
bus remains in the float state until OE# is taken to VIL.
12.11.5
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal (when in linear modes), informs the system that the last
address of a burst sequence is on the DQ data bus. For example, if a 2-double-word linear burst access is
enabled using a 16-bit DQ bus (WORD# = VIL), the IND/WAIT# signal transitions active on the second
access. If the same scenario is used, the IND/WAIT# signal has the same delay and setup timing as the DQ
pins. Also, the IND/WAIT# signal is controlled by the OE# signal. If OE# is at VIH, the IND/WAIT# signal floats
and is not driven. If OE# is at VIL, the IND/WAIT# signal is driven at VIH until it transitions to VIL indicating the
end of burst sequence. The IND/WAIT# signal timing and duration is (See Configuration Register on page 30
for more information). The following table lists the valid combinations of the Configuration Register bits that
impact the IND/WAIT# timing.
Figure 12.2 End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation
Note
Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-double-word burst,
output on rising CLD edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.
Table 12.5 Valid Configuration Register Bit Definition for IND/WAIT#
DOC
WC
CC
Definition
0
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLD edge
0
1
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
CE#
CLK
ADV#
Addresses
OE#
Data
Address 1
Address 2
Invalid
D1
D2
D3
D0
Address 1 Latched
3 Clock Delay
IND/WAIT#
VIL
VIH
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29CD016G0MFAN011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| S29CD016G0MFAN012 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| S29CD016G0MFAN013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| S29CD016G0MFFA000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0MFFA002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
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