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參數(shù)資料
| 型號： | S24163SBT |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller with 16K I2C Memory |
| 中文描述： | 精密復(fù)位控制器的I2C與16K的記憶 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 169K |
| 代理商： | S24163SBT |
S24163
7
2014 2.1 8/2/00
FIGURE 9. RANDOM ADDRESS BYTE READ MODE
Random Address Byte Read
Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issues a write command which includes the start condi-
tion and the slave address field (with the R/W bit set to
WRITE) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
S24163 to the desired address.
After the word address acknowledge is received by the
master, the master immediately reissues a start condition
followed by another slave address field with the R/W bit
set to READ. The S24163 will respond with an acknowl-
edge and then transmit the 8-data bits stored at the
addressed location. At this point, the master does not
acknowledge the transmission but does generate the stop
condition. The S24163 discontinues data transmission
and reverts to its standby power mode. See Figure 9 for
the address, acknowledge and data transfer sequence.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
S
T
A
R
T
Word Address
S
T
O
P
A
C
K
Slave Address
Slave Address
Device
Type
Address
Read/Write
0= Write
Device
Type
Address
A10,A9,A8
A10,A9,A8
SDA Bus
Activity
S
T
A
R
T
Read/Write
1= Read
A
C
K
A
C
K
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
1 0 1 0
1 0 1 0
1
0
A
10
A
9
R
W
A
8
A
9
R
W
A
10
A
8
Lack of ACK (low)
from Master
determines last
data byte to be read
1
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
24163
SDA Output Active
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Data Byte
2014 T fig09 2.0
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