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參數(shù)資料
| 型號(hào)： | S24163SBT |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller with 16K I2C Memory |
| 中文描述： | 精密復(fù)位控制器的I2C與16K的記憶 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 169K |
| 代理商： | S24163SBT |
6
S24163
2014 2.1 8/2/00
FIGURE 8. CURRENT ADDRESS BYTE READ MODE
FIGURE 7. ACKNOWLEDGE POLLING
Acknowledge Polling
When the S24163 is performing an internal WRITE opera-
tion, it will ignore any new START conditions. Since the
device will only return an acknowledge after it accepts the
START, the part can be continuously queried until an
acknowledge is issued, indicating that the internal WRITE
cycle is complete.
To poll the device, give it a START condition, followed by
a slave address for a WRITE operation (See Figure 7).
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to
“
1.
”
There are four different read
options:
1.
2.
3.
4.
Current Address Byte Read
Random Address Byte Read
Current Address Sequential Read
Random Address Sequential Read
Current Address Byte Read
The S24163 contains an internal address counter which
maintains the address of the last word accessed, incre-
mented by one. If the last address accessed (either a read
or write) was to address location n, the next read operation
would access data from address location n+1 and incre-
ment the current address pointer. When the S24163
receives the slave address field with the R/W bit set to
“
1,
”
it issues an acknowledge and transmits the 8-bit word
stored at address location n+1.
The current address byte read operation only accesses a
single byte of data. The master does not acknowledge the
transfer, but does generate a stop condition. At this point,
the S24163 discontinues data transmission. See Figure 8
for the address acknowledge and data transfer sequence.
Issue Start
Internal WRITE Cycle
In Progress;
Begin ACK Polling
Issue Slave
Address and
R/W = 0
ACK
Returned
Next
operation a
WRITE
Issue Byte
Address
Proceed with
WRITE
Issue Stop
Await Next
Command
Issue Stop
No
No
Yes (Internal WRITE Cycle is completed)
Yes
2014 ILL 9 1.0
S
T
A
R
T
S
T
O
P
Slave Address
Device
Type
Address
Read/Write
1= Read
A10,A9,A8
SDA Bus Activity
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Master sends Read
request to Slave
Slave sends
Data to Master
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
1
1
1
0
0
1
Lack of ACK (low)
from Master
determines last
data byte to be read
1
Shading Denotes
24163
SDA Output Active
A
9
A
10
R
W
A
C
K
A
8
Data Byte
2014 T fig08 2.0
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